EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 733

• Manufacturer Part Number: EVB9S12XEP100
• Description: BOARD EVAL FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S12XEP100

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.3.2.3
Read: Anytime, if AMAP = 1
Write: Anytime, if AMAP = 1
Freescale Semiconductor
Module Base + 0x0000
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
RXEDGIF
BERRIF
BERRV
Reset
BKDIF
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
7
2
1
0
W
R
RXEDGIF
Receive Input Active Edge Interrupt Flag — RXEDGIF is asserted, if an active edge (falling if RXPOL = 0,
rising if RXPOL = 1) on the RXD input occurs. RXEDGIF bit is cleared by writing a “1” to it.
0 No active receive on the receive input has occurred
1 An active edge on the receive input has occurred
Bit Error Value — BERRV reflects the state of the RXD input when the bit error detect circuitry is enabled and
a mismatch to the expected value happened. The value is only meaningful, if BERRIF = 1.
0 A low input was sampled, when a high was expected
1 A high input reassembled, when a low was expected
Bit Error Interrupt Flag — BERRIF is asserted, when the bit error detect circuitry is enabled and if the value
sampled at the RXD input does not match the transmitted value. If the BERRIE interrupt enable bit is set an
interrupt will be generated. The BERRIF bit is cleared by writing a “1” to it.
0 No mismatch detected
1 A mismatch has occurred
Break Detect Interrupt Flag — BKDIF is asserted, if the break detect circuitry is enabled and a break signal is
received. If the BKDIE interrupt enable bit is set an interrupt will be generated. The BKDIF bit is cleared by writing
a “1” to it.
0 No break signal was received
1 A break signal was received
SCI Alternative Status Register 1 (SCIASR1)
0
7
= Unimplemented or Reserved
Figure 20-6. SCI Alternative Status Register 1 (SCIASR1)
0
0
6
MC9S12XE-Family Reference Manual Rev. 1.23
Table 20-6. SCIASR1 Field Descriptions
5
0
0
0
0
4
Description
Chapter 20 Serial Communication Interface (S12SCIV5)
0
0
3
BERRV
2
0
BERRIF
0
1
BKDIF
0
0
733