EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 798

Manufacturer Part Number

EVB9S12XEP100

BOARD EVAL FOR MC9S12XEP100

Manufacturer

Freescale Semiconductor

Module and Misc Hardware

Processor To Be Evaluated

MC9S12XEP100

Data Bus Width

Interface Type

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Rohs Compliant

For Use With/related Products

MC9S12XEP100

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 22 Timer Module (TIM16B8CV2) Block Description

Read: Anytime

Write: Anytime

The 16-bit main timer is an up counter.

A full access for the counter register should take place in one clock cycle. A separate read/write for high

byte and low byte will give a different result than accessing them as a word.

Read: Anytime

Module Base + 0x0003

Module Base + 0x0004

Module Base + 0x0005

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

Output Compare 7 Data — A channel 7 event, which can be a counter overﬂow when TTOV[7] is set or a

successful output compare on channel 7, can cause bits in the output compare 7 data register to transfer to the

timer port data register depending on the output compare 7 mask register.

Output Compare 7 Data Register (OC7D)

Timer Count Register (TCNT)

Figure 22-9. Output Compare 7 Data Register (OC7D)

Figure 22-10. Timer Count Register High (TCNTH)

Figure 22-11. Timer Count Register Low (TCNTL)

MC9S12XE-Family Reference Manual Rev. 1.23

Table 22-5. OC7D Field Descriptions

Freescale Semiconductor