EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 541

• Manufacturer Part Number: EVB9S12XEP100
• Description: BOARD EVAL FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S12XEP100

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.3.2.7
Read or write: Anytime
All bits reset to zero.
Freescale Semiconductor
Module Base + 0x0007
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
TOV[7:0]
TSFRZ
TFFCA
Reset
PRNT
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
Field
7:0
5
4
3
W
R
TOV7
Timer and Modulus Counter Stop While in Freeze Mode
0 Allows the timer and modulus counter to continue running while in freeze mode.
1 Disables the timer and modulus counter whenever the MCU is in freeze mode. This is useful for emulation.
Timer Fast Flag Clear All
0 Allows the timer flag clearing to function normally.
1 A read from an input capture or a write to the output compare channel registers causes the corresponding
Note: The flags cannot be cleared via the normal flag clearing mechanism (writing a one to the flag) when
Precision Timer
0 Enables legacy timer. Only bits DLY0 and DLY1 of the DLYCT register are used for the delay selection of the
1 Enables precision timer. All bits in the DLYCT register are used for the delay selection, all bits of the PTPSR
Toggle On Overflow Bits — TOV97:0] toggles output compare pin on timer counter overflow. This feature only
takes effect when in output compare mode. When set, it takes precedence over forced output compare but not
channel 7 override events.
0 Toggle output compare pin on overflow feature disabled.
1 Toggle output compare pin on overflow feature enabled.
Timer Toggle On Overflow Register 1 (TTOV)
0
7
The pulse accumulators do not stop in freeze mode.
channel flag, CxF, to be cleared in the TFLG1 register. Any access to the TCNT register clears the TOF flag
in the TFLG2 register. Any access to the PACN3 and PACN2 registers clears the PAOVF and PAIF flags in the
PAFLG register. Any access to the PACN1 and PACN0 registers clears the PBOVF flag in the PBFLG register.
Any access to the MCCNT register clears the MCZF flag in the MCFLG register. This has the advantage of
eliminating software overhead in a separate clear sequence. Extra care is required to avoid accidental flag
clearing due to unintended accesses.
delay counter. PR0, PR1, and PR2 bits of the TSCR2 register are used for timer counter prescaler selection.
MCPR0 and MCPR1 bits of the MCCTL register are used for modulus down counter prescaler selection.
register are used for Precision Timer Prescaler Selection, and all bits of PTMCPSR register are used for the
prescaler Precision Timer Modulus Counter Prescaler selection.
TFFCA = 1.
Figure 14-10. Timer Toggle On Overflow Register 1 (TTOV)
TOV6
0
6
Table 14-7. TSCR1 Field Descriptions (continued)
MC9S12XE-Family Reference Manual Rev. 1.23
Table 14-8. TTOV Field Descriptions
TOV5
5
0
TOV4
0
4
Description
Description
TOV3
0
3
Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
TOV2
2
0
TOV1
0
1
TOV0
0
0
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