EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 386

• Manufacturer Part Number: EVB9S12XEP100
• Description: BOARD EVAL FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S12XEP100

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 10 XGATE (S12XGATEV3)
10.8.1.8
In this mode the result of an operation between two registers is stored in one of the registers used as
operands.
RD = RD ∗ RS is the general register to register format, with register RD being the first operand and RS
the second. RD and RS can be any of the 8 general purpose registers R0 … R7. If R0 is used as the
destination register, only the condition code flags are updated. This addressing mode is used only for shift
operations with a variable shift value
Examples:
10.8.1.9
In this mode the result of an operation between two or three registers is stored into a third one.
RD = RS1 ∗ RS2 is the general format used in the order RD, RS1, RS1. RD, RS1, RS2 can be any of the
8 general purpose registers R0 … R7. If R0 is used as the destination register RD, only the condition code
flags are updated. This addressing mode is used for all arithmetic and logical operations.
Examples:
10.8.1.10 Relative Addressing 9-Bit Wide (REL9)
A 9-bit signed word address offset is included in the instruction word. This addressing mode is used for
conditional branch instructions.
Examples:
10.8.1.11 Relative Addressing 10-Bit Wide (REL10)
An 10-bit signed word address offset is included in the instruction word. This addressing mode is used for
the unconditional branch instruction.
Examples:
10.8.1.12 Index Register plus Immediate Offset (IDO5)
(RS, #OFFS5) provides an unsigned offset from the base register.
Examples:
386
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
LSL
LSR
ADC
SUB
BCC
BEQ
BRA
LDB
STW
Dyadic Addressing (DYA)
Triadic Addressing (TRI)
R4,R5
R4,R5
R5,R6,R7
R5,R6,R7
REL9
REL9
REL10
R4,(R1,#OFFS5)
R4,(R1,#OFFS5)
; R4 = R4 << R5
; R4 = R4 >> R5
MC9S12XE-Family Reference Manual , Rev. 1.23
; R5 = R6 + R7 + Carry
; R5 = R6 - R7
; PC = PC + 2 + (REL9 << 1)
; PC = PC + 2 + (REL9 << 1)
; PC = PC + 2 + (REL10 << 1)
; loads a byte from (R1+OFFS5) into R4
; stores R4 as a word to (R1+OFFS5)
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