ADUC847BCPZ8-5 Analog Devices Inc, ADUC847BCPZ8-5 Datasheet - Page 25

• Manufacturer Part Number: ADUC847BCPZ8-5
• Description: IC,Data Acquisition CODEC,2-CHANNEL,LLCC,56PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC847BCPZ8-5

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 12.58MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 10x24b; D/A 1x12b, 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADUC847QSZ - KIT DEV QUICK START FOR ADUC847
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Power Control Register (PCON)
The PCON SFR contains bits for power-saving options and
general-purpose status flags as listed in Table 6.
SFR Address:
Power-On Default:
Bit Addressable:
Table 6. PCON SFR Bit Designations
Bit No.
7
6
5
4
3
2
1
0
Name
SMOD
SERIPD
INT0PD
ALEOFF
GF1
GF0
PD
-----
Description
Double UART Baud Rate.
0 = Normal, 1 = Double Baud Rate.
Serial Power-Down Interrupt Enable. If this
bit is set, a serial interrupt from either SPI
or I
mode.
INT0 Power-Down Interrupt Enable.
If this bit is set, either a level (IT0 = 0) or a
negative-going transition (IT0 = 1) on th
INT0 pin terminates power-down mode.
If set to 1, the ALE output is disabled.
General-Purpose Flag Bit.
General-Purpose Flag Bit.
Power-Down Mode Enable. If se
part enters power-down mode.
Not Implemented. Write Don’t Care.
87H
00H
No
2
C can terminate the power-down
t to 1, the
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e
ADuC845/ADuC847/ADuC848 Configuration Register
(CFG845/CFG847/CFG848)
The CFG845/CFG847/CFG848 SFR contains the bits necessary
to configure the internal XRAM and the extended SP. By default,
it configures the user into 8051 mode, that is, extended SP, and
the internal XRAM are disabled. When using in a program, use
the part name only, that is, CFG845, CFG847, or CFG8
SFR Address:
Power-On Default:
Bit Addressable:
Table 7. CFG845/CFG847/CFG848 SFR Bit Designations
Bit No.
7
6
5
4
3
2
1
0
Name
EXSP
----
----
----
----
----
----
XRAMEN
ADuC845/ADuC847/ADuC848
AFH
00H
No
Description
Extended SP Enable.
If this bit is set to 1, the stack rolls over
from SPH/SP = 00FFH to 0100H.
If this bit is cleared to 0, SPH SFR is
disabled and the stack rolls over from
SP = FFH to SP = 00H.
Not Implemented. Write Don’t Care.
Not Implemented. Write Don’t Care.
Not Implemented. Write Don’t Care.
Not Implemented. Write Don’t Care.
Not Implemented. Write Don’t Care.
Not Implemented. Write Don’t Care.
If this bit is set to 1, the internal XRAM is
mapped into the lower 2 kbytes of the
external address space.
If this bit is cleared to 0, the internal XR
is accessible and up to 16 MB of external
data memory become available. See
Figure 8.
48.
AM