ADUC847BCPZ8-5 Analog Devices Inc, ADUC847BCPZ8-5 Datasheet - Page 97

• Manufacturer Part Number: ADUC847BCPZ8-5
• Description: IC,Data Acquisition CODEC,2-CHANNEL,LLCC,56PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC847BCPZ8-5

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 12.58MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 10x24b; D/A 1x12b, 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADUC847QSZ - KIT DEV QUICK START FOR ADUC847
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 66. EXTERNAL DATA MEMORY WRITE CYCLE Parameter
t
t
t
t
t
t
t
t
t
Table 67. I
Parameter
t
t
t
t
t
t
t
t
t
t
t
____________________________________________
1
WLWH
AVLL
LLAX
LLWL
AVWL
QVWX
QVWH
WHQX
WHLH
L
H
SHD
DSU
DHD
RSU
PSU
BUF
R
F
SUP
Input filtering on both the SCLOCK and SDATA inputs suppresses noise spikes less than 50 ns.
1
2
C-COMPATIBLE INTERFACE TIMING Parameter
WR Pulse Width
Address Valid After ALE Low
Address Hold After ALE Low
ALE Low to RD or WR Low
Address Valid to RD or WR Low
Data Valid to WR Transition
Data Setup Before WR
Data and Address Hold After WR
RD or WR High to ALE High
SCLCK Low Pulse Width
SCLCK High Pulse Width
Start Condition Hold Time
Data Setup Time
Data Hold Time
Setup Time for Repeated Start
Stop Condition Setup Time
Bus Free Time Between a Stop Condition and a Start Condition
Rise Time of Both SCLCK and SDATA
Fall Time of Both SCLCK and SDATA
Pulse Width of Spike Suppressed
PORT 2 (O)
PSEN (O)
ALE (O)
WR (O)
t
AVLL
A16 A23
A0 A7
t
Figure 74. External Data Memory Write Cycle
LLAX
t
AVWL
t
LLWL
Rev. B | Page 97 of 108
Min
65
60
65
190
60
120
380
60
12.58 MHz Core Clock
t
QVWX
DATA
t
t
V8 A15
WLWH
QVWH
Max
130
Min
130
120
135
375
120
250
755
125
ADuC845/ADuC847/ADuC848
t
t
WHLH
WHQX
6.29 MHz Core Clock
Min
1.3
0.6
0.6
100
0.6
0.6
1.3
Max
260
Max
0.9
300
300
50
Unit
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns