ADUC847BCPZ8-5 Analog Devices Inc, ADUC847BCPZ8-5 Datasheet - Page 67

• Manufacturer Part Number: ADUC847BCPZ8-5
• Description: IC,Data Acquisition CODEC,2-CHANNEL,LLCC,56PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC847BCPZ8-5

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 12.58MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 10x24b; D/A 1x12b, 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADUC847QSZ - KIT DEV QUICK START FOR ADUC847
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DUAL DATA POINTERS
The parts incorporate two data pointers. The second data
pointer is a shadow data pointer and is selected via the data
pointer control SFR (DPCON). DPCON features automatic
hardware post-increment and post-decrement as well as an
automatic data pointer toggle.
Table 42. DPCON SFR Bit Designations
Bit No.
7
6
5, 4
3, 2
1
0
Note the following:
•
•
To illustrate the operation of DPCON, the following code copies
256 bytes of code memory at Address D000H into XRAM,
starting from Address 0000H.
The Dual Data Pointer section is the only place in which
main and shadow data pointers are distinguished.
Whenever the DPTR is mentioned elsewhere in this data
sheet, active DPTR is implied.
Only the MOVC/MOVX @DPTR instructions
automatically post-increment and post-decrement the
DPTR. Other MOVC/MOVX instructions, such as MOVC
PC or MOVC @Ri, do not cause the DPTR to automatically
post-increment and post-decrement.
Name
----
DPT
DP1m1, DP1m0
DP0m1, DP0m0
----
DPSEL
Description
Not Implemented. Write Don’t Care.
Data Pointer Automatic Toggle Enable.
Cleared by the user to disable autoswapping of the DPTR.
Set in user software to enable automatic toggling of the DPTR after each MOVX or MOVC instruction.
Shadow Data Pointer Mode. These bits enable extra modes of the shadow data pointer operation, allowing
more compact and more efficient code size and execution.
DP1m1
0
0
1
1
Main Data Pointer Mode. These bits enable extra modes of the main data pointer operation, allowing more
compact and more efficient code size and execution.
DP0m1
0
0
1
1
Not Implemented. Write Don’t Care.
Data Pointer Select.
Cleared by the user to select the main data pointer. This means that the contents of this 24-bit register are
placed into the DPL, DPH, and DPP SFRs.
Set by the user to select the shadow data pointer. This means that the contents of a separate 24-bit register
appear in the DPL, DPH, and DPP SFRs.
DP1m0
0
1
0
1
DP0m0
0
1
0
1
Behavior of the Shadow Data Pointer
8052 behavior.
DPTR is post-incremented after a MOVX or a MOVC instruction.
DPTR is post-decremented after a MOVX or MOVC instruction.
DPTR LSB is toggled after a MOVX or MOVC instruction. (This instruction can be useful for
moving 8-bit blocks to/from 16-bit devices.)
Behavior of the Main Data Pointer
8052 behavior.
DPTR is post-incremented after a MOVX or a MOVC instruction.
DPTR is post-decremented after a MOVX or MOVC instruction.
DPTR LSB is toggled after a MOVX or MOVC instruction. (This instruction is useful for
moving 8-bit blocks to/from 16-bit devices.)
Rev. B | Page 67 of 108
DPCON—Data Pointer Control SFR
SFR Address:
Power-On Default:
Bit Addressable:
MOVELOOP: CLR A
MOV DPTR,#0
MOV DPCON,#55H
MOV DPTR,#0D000H ;DPTR = D000H
MOVC A,@A+DPTR
MOVX @DPTR,A
MOV A, DPL
JNZ MOVELOOP
ADuC845/ADuC847/ADuC848
A7H
00H
No
;Main DPTR = 0
;Select shadow DPTR
;DPTR1 increment mode
;DPTR0 increment mode
;DPTR auto toggling ON
;Get data
;Post Inc DPTR
;Swap to Main DPTR(Data)
;Put ACC in XRAM
;Increment main DPTR
;Swap Shadow DPTR(Code)