ADUC847BCPZ8-5 Analog Devices Inc, ADUC847BCPZ8-5 Datasheet - Page 28

IC,Data Acquisition CODEC,2-CHANNEL,LLCC,56PIN,PLASTIC

ADUC847BCPZ8-5

Manufacturer Part Number
ADUC847BCPZ8-5
Description
IC,Data Acquisition CODEC,2-CHANNEL,LLCC,56PIN,PLASTIC
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC8xxr
Datasheet

Specifications of ADUC847BCPZ8-5

Core Processor
8052
Core Size
8-Bit
Speed
12.58MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
POR, PSM, PWM, Temp Sensor, WDT
Number Of I /o
34
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
4.75 V ~ 5.25 V
Data Converters
A/D 10x24b; D/A 1x12b, 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
56-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-ADUC847QSZ - KIT DEV QUICK START FOR ADUC847
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ADuC845/ADuC847/ADuC848
Thi
Thi
pro
whi
fully
grammin
s offset i
s average
le an asy
reflecte
t
SETTLE
s remove
nchron
d until t
g of th
by 2 m
=
f
ADC
2
e ADC is twice the no
ous step change on th
eans that the settling
he third subsequent
d by performing a r
=
2
×
t
ADC
SAMPLE 1
SAMPLE 1
NO/INVALID
NO OUTPUT
OUTPUT
Figure 14. ADC Settlin
unnin
outpu
Figure 13. ADC Settling Time Following a Synchronous Change with
time t
rma
e ana
SAMPLE 2
SAMPLE 2
SAMPLE 1 + SAMPLE 2
SAMPLE 1 + SAMPLE 2
l conver
VALID OUTPUT
VALID OUTPUT
log inp
g avera
t. See
o any
2
2
Figure
chang
sion
ut is n
SYNC
SAMPLE 3
SAMPLE 3
ge of
(I.E.
SAMPLE 2 + SAMPLE 3
(I.E. D
SAMPLE 2 + S
C
VALID OU
VALID OUTPUT
HRONOU
g Time Following an Asynchronous Change with
time,
HANNEL
ASYNCH
ISCONT
2.
e in
ot
13.
Rev. B | Page 28 of 108
2
2
Chop Enabled
Chop Enabled
S CHA
TPUT
INUO
CHA
AMPLE 3
SAMPLE 4
RON
SAMPLE 4
SAMPLE 3 + SAMPLE 4
SAMPLE 3 + SAMPLE 4
UNSETT
N
US INPUT
O
NGE
GE)
US CHA
NO OUTPUT
LED OUTPUT
2
2
NGE
CHAN
SAMPLE 5
SAMPLE 5
SAMPLE 4 + SAMPLE 5
SAMPLE 4 + SAMPLE 5
Th
a de
rms a
Ta
typi
and a common-mode voltage of 2.5 V. Note that the con-
version time increases by 0.732 ms for each increment in
UNSETTLED OUTPUT
ble 10, Ta
VALID OUTP
GE)
e allowab
cal and
fault of
nd pe
2
2
SAMPLE 6
SAMPLE 6
ak-to-p
SAMPLE 5 + SAMP
SAMPLE 5 + SAMPLE 6
gene
69 (45H). The corr
ble 11
le ra
UT
VALID OUTPUT
VALID OUTPUT
rated at a
nge for S
, Table 1
eak no
2
2
F (ch
ise pe
LE 6
2, a
diffe
nd Table
op enab
espond
rential i
rforma
ing co
nces
led) is
nput v
13. T
are sho
he num
nversi
oltage
13 to
on ra
wn in
255 w
of 0
bers
tes,
V
SF.
are
ith

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