ADUC847BCPZ8-5 Analog Devices Inc, ADUC847BCPZ8-5 Datasheet - Page 81

• Manufacturer Part Number: ADUC847BCPZ8-5
• Description: IC,Data Acquisition CODEC,2-CHANNEL,LLCC,56PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC847BCPZ8-5

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 12.58MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 10x24b; D/A 1x12b, 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADUC847QSZ - KIT DEV QUICK START FOR ADUC847
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(SHIFT CLOCK)
(SCON.1)
Mode 0 (8-Bit Shift Register Mode)
Mode 0 is selected by clearing both the SM0 and SM1 bits in the
SFR SCON. Serial data enters and exits through RxD. TxD
outputs the shift clock. Eight data bits are transmitted or
received. Transmission is initiated by any instruction that writes
to SBUF. The data is shifted out of the RxD line. The 8 bits are
transmitted with the least significant bit (LSB) first.
Reception is initiated when the receive enable bit (REN) is 1
and the receive interrupt bit (RI) is 0. When RI is cleared, the
data is clocked into the RxD line, and the clock pulses are
output from the TxD line as shown in Figure 58.
Mode 1 (8-Bit UART, Variable Baud Rate)
Mode 1 is selected by clearing SM0 and setting SM1. Each data
byte (LSB first) is preceded by a start bit (0) and followed by a
stop bit (1). Therefore, 10 bits are transmitted on TxD or are
received on RxD. The baud rate is set by the Timer 1 or Timer 2
overflow rate, or a combination of the two (one for transmission
and the other for reception).
Transmission is initiated by writing to SBUF. The write to SBUF
signal also loads a 1 (stop bit) into the 9th bit position of the
transmit shift register. The data is output bit-by-bit until the
stop bit appears on TxD and the transmit interrupt flag (TI) is
automatically set as shown in Figure 59.
Reception is initiated when a 1-to-0 transition is detected on
RxD. Assuming that a valid start bit is detected, character
reception continues. The start bit is skipped and the 8 data bits
are clocked into the serial port shift register. When all 8 bits
have been clocked in, the following events occur:
•
•
•
(DATA OUT)
TxD
The 8 bits in the receive shift register are latched into SBUF.
The 9th bit (stop bit) is clocked into RB8 in SCON.
The receiver interrupt flag (RI) is set.
TI
RxD
TxD
START
BIT
D0
DATA BIT 0
D1
Figure 58. 8-Bit Shift Register Mode
Figure 59. 8-Bit Variable Baud Rate
D2
DATA BIT 1
D3
D4
D5
I.E., READY FOR MORE DATA
DATA BIT 6
D6
SET INTERRUPT
D7
STOP BIT
DATA BIT 7
Rev. B | Page 81 of 108
All of the following conditions must be met at the time the final
shift pulse is generated:
•
•
•
If any of these conditions is not met, the received frame is
irretrievably lost, and RI is not set.
Mode 2 (9-Bit UART with Fixed Baud Rate)
Mode 2 is selected by setting SM0 and clearing SM1. In this
mode, the UART operates in 9-bit mode with a fixed baud rate.
The baud rate is fixed at Core_Clk/64 by default, although by
setting the SMOD bit in PCON, the frequency can be doubled
to Core_Clk/32. Eleven bits are transmitted or received: a start
bit (0), 8 data bits, a programmable 9th bit, and a stop bit (1).
The 9th bit is most often used as a parity bit, although it can be
used for anything, including a ninth data bit if required.
To transmit, the 8 data bits must be written into SBUF. The
ninth bit must be written to TB8 in SCON. When transmission
is initiated, the 8 data bits (from SBUF) are loaded into the
transmit shift register (LSB first). The contents of TB8 are
loaded into the 9th bit position of the transmit shift register.
The transmission starts at the next valid baud rate clock. The
TI flag is set as soon as the stop bit appears on TxD.
Reception for Mode 2 is similar to that of Mode 1. The 8 data
bytes are input at RxD (LSB first) and loaded onto the receive
shift register. When all 8 bits have been clocked in, the
following events occur:
•
•
•
All of the following conditions must be met at the time the final
shift pulse is generated:
•
•
•
If any of these conditions is not met, the received frame is
irretrievably lost, and RI is not set.
RI = 0
Either SM2 = 0 or SM2 = 1
Received stop bit = 1
The 8 bits in the receive shift register are latched into SBUF.
The 9th data bit is latched into RB8 in SCON.
The receiver interrupt flag (RI) is set.
RI = 0
Either SM2 = 0 or SM2 = 1
Received stop bit = 1
ADuC845/ADuC847/ADuC848