ADUC847BCPZ8-5 Analog Devices Inc, ADUC847BCPZ8-5 Datasheet - Page 91

• Manufacturer Part Number: ADUC847BCPZ8-5
• Description: IC,Data Acquisition CODEC,2-CHANNEL,LLCC,56PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC847BCPZ8-5

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 12.58MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 10x24b; D/A 1x12b, 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADUC847QSZ - KIT DEV QUICK START FOR ADUC847
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In addition to the basic UART connections, users also need a
way to trigger the chip into download mode. This is
accomplished via a 1 kΩ pull-down resistor that can be
jumpered onto the PSEN pin, as shown in Figure 70. To get the
parts into download mode, connect this jumper and power-
cycle the device (or manually reset the device, if a manual reset
button is available), and it is ready to receive a new program
serially. With the jumper removed, the device powers on in
normal mode (and runs the program) whenever power is cycled
or RESET is toggled. Note that PSEN is normally an output and
that it is sampled as an input only on the falling edge of RESET,
that is, at power-on or upon an external manual reset. Note also
that if any external circuitry unintentionally pulls PSEN low
during power-on or reset events, it could cause the chip to enter
NOTES
1. EXTERNAL UART TRANSCEIVER INTEGRATED IN SYSTEM OR AS PART
200µA/400µA
EXCITATION
RS-232 INTERFACE
OF AN EXTERNAL DONGLE AS DESCRIBED IN APPLICATION NOTE uC006.
CURRENT
0.1µF
0.1µF
RTD
5.6kΩ
R
REF
C1+
V+
C1–
C2+
C2–
V–
T2OUT
R2IN
1
AV
RESET ACTIVE HIGH.
ADM3202
(NORMALLY OPEN)
0.1µF
DD
R1OUT
R2OUT
T1OUT
DV
R1IN
GND
T1IN
T2IN
V
DD
CC
11
56
4
5
6
7
8
1
Figure 70. UART Connectivity in Typical System
P1.6/I
AV
AGND
REFIN+
P1.0/AIN1
P1.1/AIN2
0.1µF
AGND
REFIN–
DD
DV
17 18
EXC
ADuC845/ADuC847/ADuC848
DD
1/AIN7
Rev. B | Page 91 of 108
19
LFCSP PACKAGE
22 36
DV
STANDARD D-TYPE
DD
CONNECTOR TO
SERIAL COMMS
51
PC HOST
0.1µF
23
download mode and fail to begin user code execution. To
prevent this, ensure that no external signals are capable of
pulling the PSEN pin low, except for the external PSEN jumper
itself or the method of download entry in use during a reset or
power-cycle condition.
Embedded Serial Port Debugger
From a hardware perspective, entry to serial port debug mode is
identical to the serial download entry sequence described
previously. In fact, both serial download and serial port debug
modes are essentially one mode of operation used in two
different ways.
DOWNLOAD/DEBUG
(NORMALLY OPEN)
37
1
2
3
4
5
6
7
8
9
ENABLE JUMPER
1kΩ
38
50
44
XTAL2
XTAL1
43
1kΩ
DV
35
34
DD
ADuC845/ADuC847/ADuC848
32.768kHz
2-PIN HEADER FOR
EMULATION ACCESS
(NORMALLY OPEN)