ADUC847BCPZ8-5 Analog Devices Inc, ADUC847BCPZ8-5 Datasheet - Page 80

IC,Data Acquisition CODEC,2-CHANNEL,LLCC,56PIN,PLASTIC

ADUC847BCPZ8-5

Manufacturer Part Number
ADUC847BCPZ8-5
Description
IC,Data Acquisition CODEC,2-CHANNEL,LLCC,56PIN,PLASTIC
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC8xxr
Datasheet

Specifications of ADUC847BCPZ8-5

Core Processor
8052
Core Size
8-Bit
Speed
12.58MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
POR, PSM, PWM, Temp Sensor, WDT
Number Of I /o
34
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
4.75 V ~ 5.25 V
Data Converters
A/D 10x24b; D/A 1x12b, 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
56-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-ADUC847QSZ - KIT DEV QUICK START FOR ADUC847
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ADuC845/ADuC847/ADuC848
UART SERIAL INTERFACE
The serial port is full duplex, meaning that it can transmit and
receive simultaneously. It is also receive buffered, meaning that
it can begin receiving a second byte before a previously received
byte is read from the receive register. However, if the first byte is
still not read by the time reception of the second byte is complete,
the first byte is lost. The physical interface to the serial data
network is via Pins RxD(P3.0) and TxD(P3.1), while the SFR
interface to the UART comprises SBUF and SCON, as described
below.
Table 54. SCON SFR Bit Designations
Bit No.
7, 6
5
4
3
2
1
0
SBUF—UART Serial Port Data Register
SFR Address:
Power-On Default:
Bit Addressable:
Name
SM0, SM1
SM2
REN
TB8
RB8
TI
RI
99H
00H
No
Description
UART Serial Mode Select Bits. These bits select the serial port operating mode as follows:
SM0
0
0
1
1
Multiprocessor Communication Enable Bit.
Enables multiprocessor communication in Modes 2 and 3.
In Mode 0, SM2 should be cleared.
In Mode 1, if SM2 is set, RI is not activated if a valid stop bit was not received. If SM2 is cleared, RI is set as soon as
the byte of data is received.
In Modes 2 or 3, if SM2 is set, RI is not activated if the received ninth data bit in RB8 is 0.
If SM2 is cleared, RI is set as soon as the byte of data is received.
Serial Port Receive Enable Bit.
Set by user software to enable serial port reception.
Serial Port Transmit (Bit 9).
The data loaded into TB8 is the ninth data bit transmitted in Modes 2 and 3. Cleared by user software to disable
serial port reception.
Serial Port Receiver Bit 9.
The ninth data bit received in Modes 2 and 3 is latched into RB8. For Mode 1, the stop bit is latched into RB8.
Serial Port Transmit Interrupt Flag.
Set by hardware at the end of the eighth bit in Mode 0, or at the beginning of the stop bit in Modes 1, 2, and 3.
TI must be cleared by user software.
Serial Port Receive Interrupt Flag.
Set by hardware at the end of the eighth bit in Mode 0, or halfway through the stop bit in Modes 1, 2, and 3.
RI must be cleared by software.
SM1
0
1
0
1
Selected Operating Mode.
Mode 0: Shift register, fixed baud rate (Core_Clk/2).
Mode 1: 8-bit UART, variable baud rate.
Mode 2: 9-bit UART, fixed baud rate (Core_Clk/32) or (Core_Clk/16).
Mode 3: 9-bit UART, variable baud rate.
Rev. B | Page 80 of 108
SBUF SFR
Both the serial port receive and transmit registers are accessed
through the SBUF SFR (SFR address = 99H). Writing to SBUF
loads the transmit register, and reading SBUF accesses a
physically separate receive register.
SCON UART—Serial Port Control Register
SFR Address:
Power-On Default:
Bit Addressable:
98H
00H
Yes

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