ADUC847BCPZ8-5 Analog Devices Inc, ADUC847BCPZ8-5 Datasheet - Page 83

• Manufacturer Part Number: ADUC847BCPZ8-5
• Description: IC,Data Acquisition CODEC,2-CHANNEL,LLCC,56PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC847BCPZ8-5

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 12.58MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 10x24b; D/A 1x12b, 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADUC847QSZ - KIT DEV QUICK START FOR ADUC847
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timer 3 Generated Baud Rates
The high integer dividers in a UART block mean that high
speed baud rates are not always possible. Also, generating baud
rates requires the exclusive use of a timer, rendering it unusable
for other applications when the UART is required. To address
this problem, the ADuC845/ADuC847/ADuC848 have a
dedicated baud rate timer (Timer 3) specifically for generating
highly accurate baud rates. Timer 3 can be used instead of
Timer 1 or Timer 2 for generating very accurate high speed
UART baud rates including 115200 and 230400. Timer 3 also
allows a much wider range of baud rates to be obtained. In fact,
every desired bit rate from 12 bps to 393216 bps can be
generated to within an error of ±0.8%. Timer 3 also frees up the
other three timers, allowing them to be used for different
applications. A block diagram of Timer 3 is shown in Figure 61.
Two SFRs (T3CON and T3FD) are used to control Timer 3.
T3CON is the baud rate control SFR, allowing Timer 3 to be
used to set up the UART baud rate, and to set up the binary
divider (DIV).
Table 55. T3CON SFR Bit Designations
Bit No.
7
6
5
4
3
2, 1, 0
FRACTIONAL
DIVIDER
÷ (1 + T3FD/64)
CORE
Name
T3BAUDEN
DIV2, DIV1, DIV0
÷ 2
÷ 16
CLK
Figure 61. Timer 3, UART Baud Rate
DIV
T3 Rx/Tx
CLOCK
Rx CLOCK
TIMER 1/TIMER 2
1
1
Tx CLOCK
T3UARTBAUD Enable.
Not Implemented. Write Don’t Care.
Not Implemented. Write Don’t Care.
Not Implemented. Write Don’t Care.
Not Implemented. Write Don’t Care.
Binary Divider
0
0
Description
Set to enable Timer 3 to generate the baud rate. When set, PCON.7, T2CON.4, and T2CON.5 are
ignored. Cleared to let the baud rate be generated as per a standard 8052.
DIV2
0
0
0
0
1
1
1
TIMER 1/TIMER 2
DIV1
0
0
1
1
0
0
1
T3EN
Rx CLOCK
Tx CLOCK
DIV0
0
1
0
1
0
1
0
Rev. B | Page 83 of 108
Binary Divider 0. See Table 57.
Binary Divider 1. See Table 57.
Binary Divider 2. See Table 57.
Binary Divider 3. See Table 57.
Binary Divider 4. See Table 57.
Binary Divider 5. See Table 57.
Binary Divider 6. See Table 57.
The appropriate value to write to the DIV2-1-0 bits can be
calculated using the following formula where f
PLLCON SFR. Note that the DIV value must be rounded down.
T3FD is the fractional divider ratio required to achieve the
required baud rate. The appropriate value for T3FD can be
calculated with the following formula:
Note that T3FD should be rounded to the nearest integer. Once
the values for DIV and T3FD are calculated, the actual baud
rate can be calculated with the following formula:
For example, to get a baud rate of 9600 while operating at a core
clock frequency of 1.5725 MHz, that is, CD = 3,
Note that the DIV result is rounded down.
Therefore, the actual baud rate is 9588 bps, which gives an error
of 0.12%.
The T3CON and T3FD registers are used to control Timer 3.
T3CON – Timer 3 Control Register
SFR Address:
Power-On Default:
Bit Addressable:
DIV =
T3FD =
Actual Baud Rate =
DIV = log(1572500/(16 × 9600))/log2 = 3.35 = 3
T3FD = (2 × 1572500)/(2
log
2
×
⎛
⎜ ⎜
⎝
2
Core
Core
DIV
ADuC845/ADuC847/ADuC848
16
−1
Clock
Clock
9EH
00H
No
×
log
×
Baud
2
Baud
(
×
) 2
2
Frequency
Frequency
Core
DIV
3−1
Rate
Rate
−
× 9600) − 64 = 18 = 12H
1
Clock
×
(
T3FD
⎞
⎟ ⎟
⎠
− 64
Frequency
+
64
CORE
)
is defined in