ADUC847BCPZ8-5 Analog Devices Inc, ADUC847BCPZ8-5 Datasheet - Page 34

• Manufacturer Part Number: ADUC847BCPZ8-5
• Description: IC,Data Acquisition CODEC,2-CHANNEL,LLCC,56PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC847BCPZ8-5

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 12.58MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 10x24b; D/A 1x12b, 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADUC847QSZ - KIT DEV QUICK START FOR ADUC847
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC845/ADuC847/ADuC848
enabled for any SF word that yields an ADC throughput that i
less than 20 Hz with chop enabled (SF ≥ 68 decimal).
ADC CHOPPING
The ADCs on the ADuC845/ADuC847/ADuC848 implement a
chopping scheme whereby the ADC repeatedly reverses its
inputs. The decim
therefore, have a positive and negative offset term in
a result, a final summing stage is included in each A
each output word from the filter is summed and averaged with
the previous filter output to produce a new valid output result
to be written to the ADC data SFRs. The ADC throughput or
update rate is listed in Table 29. The chopping scheme
porated into the parts results in
drift specifications, and is extremely beneficial in applications
where drift, noise rejection, and optimum EMI performan
important. ADC chop can be disabled via the chop bit in the
ADCMODE SFR (ADCM
hig ) disables chop mode.
CAL
The
mod
ADC
befo
cali ration coefficients for both the primary and auxiliary
(AD
speci
rese
dow
space. To facilitate user calibration, each of the primary and
auxiliary (ADuC845 only) ADCs have dedicated calibration
control SFRs, which are described in the ADC SFR Interface
section. Once a user initiates a calibration procedure, the factory
calibration values that were initially downloaded during the
power-on sequence to the ADC calibration S
The ADC to be calibrated must be enabled via
bits in the ADCMODE register.
Even though an internal offset calibration mode is described in
this section, note that the ADCs can be chopped. This chopping
scheme inherently minimizes offset errors and means that an
offset calibration should never be required. Also, because
factory 5 V/25°C gain calibration coefficients are automatically
present at power-on, an internal full-scale calibration is requ
only if the part is operated at 3 V or at temperatures significantly
different from 25°C.
If the part is operated in chop disabled mode, a calibration
need to be done with every gain range change that occurs vi
the PGA.
The ADuC845/ADuC847/ADuC848 each offer internal or
system calibration facilities. For full calibration to occur on the
selected ADC, the calibration logic must record the modulator
h
b
t, these factory calibration registers are automatically
ADuC845
re it leaves the factory. The resulting offset and gain
nloaded to the ADC calibration registers in the part’s
uC845 only) ADCs are stored on-chip in manufact
es that can be programmed via the mode bits in the
fic Flash/EE memory locations. At power-on or after a
IBRATION
MODE SFR detailed in Table 24. Every part is calibrated
/ADuC847/ADuC848 incorporate four calibration
ated digital output words from the Sinc
ODE.3). Setting this bit to 1 (logic
excellent dc offset and offset
FRs are overwritten.
the ADC enable
DC so that
cluded. As
incor-
uring-
3
SFR
ce are
filter,
ired
may
a
Rev. B | Page 34 of 108
s
output for two input conditions: zero-scale and full-scale points
These points are derived by performing a conversion on the
different input voltages (zero-scale and full-scale) provided to the
input of the modulator during calibration. The result of the
zero-scale calib
calibration registers for the appropriate ADC. The r
full-scale calibration conversion is stored in the gain calibratio
registers for the appropriate ADC. With these readings, the
calibration logic can calculate the offset and the gain slope fo
the input-to-output transfer function of the converter.
During an internal zero-scale or full-scale calibration, the
respective zero-scale input or full-scale input is automatically
connected to the ADC inputs internally. A system calibration,
however, expects the system
voltages to be applied externally to the ADC pins by the user
before the calibration mode is initiated. In this way, external
errors are taken into account and minimized. Note that all
ADuC845/ADuC847/ADuC848 ADC calibrations are carried
out at the user-selected SF word update rate. To optimize
calibration accuracy, it is recommended that the slowest possible
update rate be used.
Internally in the
being used to scale the words coming out of the digital filter.
The offset calibration coefficient is subtracted from the result
prior to the multiplication by the gain coefficient.
From an operational point of view, a calibration should be
treated just like an ordinary ADC conversion. A zero-scale
calibration (if required) should always be carried out before a
full-scale calibration. System software should monitor the
relevant ADC RDY0/1 bit in the ADCSTAT SFR to determine
the end of calibration by using a polling sequence or an interrup
driven routine. If required, the NOEXREF0/1 bits can be moni
tored to detect unconnected or low voltage errors in the referenc
during conversion. In the event of the reference becoming
disconnect
calibration is immediately halted and no write to the calibration
SFRs takes pla
Internal Calibration Example
With chop e
never be required, although a full-scale or gain calibration may
be required. However, if a full internal calibration is required,
the procedure should be to select a PGA gain of 1 (±2.56 V) and
perform a zero-scale calibration (MD2...0 = 100B in the
ADCMODE register). Next, select and perform full-scale
calibration by setting MD2...0 = 101B in the ADCMODE SFR.
Now select the desired PGA range and perform a zero-scale
calibration again (MD2..0 = 100B in ADCMODE) at the new
PGA range. The reason for the double zero-scale calibration is
that the internal calibration procedure for full-scale calibration
automatically selects the reference in voltage at PGA = 1.
ed, causing a NOXREF flag during a calibration, the
nabled, a zero-scale or offset calibration
ce.
ration conversion is stored in the offset
parts, the coefficients are normalized before
zero-scale and system full-scale
esult of the
should
r
n
t
-
e
.