ADUC847BCPZ8-5 Analog Devices Inc, ADUC847BCPZ8-5 Datasheet - Page 33

• Manufacturer Part Number: ADUC847BCPZ8-5
• Description: IC,Data Acquisition CODEC,2-CHANNEL,LLCC,56PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC847BCPZ8-5

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 12.58MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 10x24b; D/A 1x12b, 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADUC847QSZ - KIT DEV QUICK START FOR ADUC847
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

and a measurement of the input voltage on the analog input
channel can be taken. When the resulting voltage meas
full scale, the transduce
measured is 0 V, this i
short circuit. The current sources work over the normal
absolute input voltage range specifications.
REFERENCE DETECT CIRCUIT
The main and auxiliary (ADuC845 only) ADCs can be config-
ured to allow the use of the internal band gap reference or an
external reference that is applied to the REFIN± pins by means
of the XREF0/1 bit in the Control Registers AD0CON2 and
AD1CON (ADuC845 only). A reference detection circuit is
provided to detect whether a valid voltage is applied to the
REFIN± pins. This feature arose in connection with strain-gage
sensors in weigh scales where the reference and signal are
provided via a cable from the remote sensor. It is desirable to
detect whether the cable is disconnected. If either of the pins is
floating or if the applied vol
flag (NOXREF) is set in t
conversion results a
updated if a calibration is in progress.
Note that the reference detect does not look at REFIN2± pins.
If, during either an offset or gain calibration, the NOEXRE
becomes active, indicating an incorrect V
relevant calibration register is inhibited to avoid loading
incorrect data into these registers, and the appropriate bits in
ADCSTAT (ERR0 or ERR1) are set. If the user needs to verify
that a valid reference is in place every time a calibration is
performed, the status of the ERR0 and ERR1 bits should be
checked at the end of every calibration cycle.
SINC FILTER REGISTER (SF)
The number entered into the SF register sets the decimation
factor of the Sinc
The range of operation of the SF w
ADC chop is on or off. With chop disabled, the minimum SF
word is 3 and the maximum is 255. This gives an ADC through-
put rate from 16.06 Hz to 1.365 kHz. With chop enabled, the
minimum SF word is 13 (all values lower than 13 are clamped
to 13) and the maximum is 255. This gives an ADC throug
rate of 5.4 Hz to 105 Hz. See the f
description preceding section.
An additional feature
positioned in the frequency response at 60 Hz. This gives
simultaneous 60 Hz rejection to whatever notch is defined by
the SF filter. This 60 Hz filter is enabled via the REJ60 bit in th
ADCMOD
for SF words ≥ 68; otherwise, ADC errors occur, and, the no
is best used with an SF word of 82d giving simultaneous 50 Hz
and 60 Hz rejection. This function is useful only with an ADC
E register (ADCMODE.6). The notch is valid only
3
filter for the ADC. See Table 28 and Table 29.
re clamped, and calibration registers are not
ndicates that the transducer has gone
of the Sinc
r has gone open circuit. When the voltage
he ADC status register (ADCSTAT),
tage is below a specified threshold, a
3
ADC
filter is a second notch filter
ord depends on whether
equation in the ADC
REF
, updating the
ured is
F bit
hput
Rev. B | Page 33 of 108
tch
e
clock (modulator rate) of 32.768 kHz. During calibration, the
current (user-written) value of the SF register is used.
Σ-∆ MODULATOR
A Σ-∆ ADC usually consists of two main blocks, an ana
modulator, and a digital filter. For the ADuC845/ADuC847/
ADuC848, the analog modulator consists of a difference
amplifier, an integrator block, a comparator, and a feedback
DAC as shown in Figure 16.
ANALOG
In operation, the analog signal is fed to the difference amplifier
along with the output from the feedback DAC. The difference
between these two signals is integrated and fed to the comparator.
The output from the comparator provides the input to the feed-
back DAC so the system f unctions as a negative feedback loop
that tries to minimize the difference signal. The digital data th
represents the analog input voltage is contained in the duty
cycle of the pulse train appearing at the output of the comparato
This duty cycle data can be recovered as a data-wor
subsequent digital filter stage. The sampling frequency of the
modulator loop is many times higher than the bandwidth o
input signal. The integrator in the modulator shapes the
quantization noise (that results from the analog-to-digital
conversion) so that the noise is pushed toward one-half of t
modulator frequency.
DIGITAL FILTER
The output of the ∑-∆ modulator feeds directly into the digital
filter. The digital filter then band-limits the response to a
frequency significantly lower than one-half of the modulator
frequency. In this manner, the 1-bit output of the comparator is
translated into a ba
The ADuC845/ADuC847/ADuC
or [(SINx)/x]
quantization noise introduced at the modulator. The cutoff
frequency and decimated output data rate of the filter are
programmable via the SF (Sinc filter) SFR as listed in Table 28
and Table 29.
Figure 22, Figure 23, Figure 24, and Figure 25 show the frequency
response of the ADC, yielding an overall output rate of 16.6 H
with chop enabled and 50 Hz with chop disabled. Also detailed
in these plots is the effect of the fixed 60 Hz drop-in notch filter
(REJ60 bit, ADCMODE.6). This fixed filter can be enabled or
disabled by setting or clearing the REJ60 bit in the ADCMO
register (ADCMODE.6). This 60 Hz drop-in notch filter can be
INPUT
DIFFERENCE
Figure 16. Σ-∆ Modulator Simplified Block Diagram
3
AMP
filter whose primary function is to remove the
nd-limited, low noise output from the part.
ADuC845/ADuC847/ADuC848
INTEGRATOR
DAC
848 filter is a low-pass, Sinc
COMPARATOR
d by using a
HIGH
FREQUEN
BIT STREAM
TO DIGITAL
FILTER
log
he
CY
f the
DE
3
at
z
r.