LAN91C111I-NS SMSC, LAN91C111I-NS Datasheet - Page 123

IC ETHERNET CTLR MAC PHY 128-QFP

LAN91C111I-NS

Manufacturer Part Number
LAN91C111I-NS
Description
IC ETHERNET CTLR MAC PHY 128-QFP
Manufacturer
SMSC
Type
Single Chip MAC and PHYr
Datasheet

Specifications of LAN91C111I-NS

Controller Type
Ethernet Controller, MAC/PHY
Interface
Serial EEPROM
Voltage - Supply
3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
128-QFP
Product
Ethernet Controllers
Number Of Transceivers
1
Standard Supported
IEEE 802.3 or IEEE 802.3u
Data Rate
10 Mbps or 100 Mbps
Supply Voltage (max)
5 V
Supply Voltage (min)
0 V
Supply Current (max)
140 mA
Maximum Operating Temperature
+ 85 C
Ethernet Connection Type
100BASE-T or 100BASE-T4 or 100BASE-TX or 10BASE-T
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
638-1014

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LAN91C111I-NS
Manufacturer:
RECOM
Quantity:
1 000
Part Number:
LAN91C111I-NS
Manufacturer:
SMSC
Quantity:
1 000
Part Number:
LAN91C111I-NS
Manufacturer:
Standard
Quantity:
6 916
Part Number:
LAN91C111I-NS
Manufacturer:
Microchip Technology
Quantity:
10 000
10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
SMSC LAN91C111 REV C
SYM
t42
t43
t44
t45
t46
t47
t48
t49
t50
t51
t52
t53
t54
t55
t56
t57
t58
t59
PARAMETER
NLP Transmit Link Pulse Width
NLP Transmit Link Pulse Period
NLP Receive Link Pulse Width Required
For Detection
NLP Receive Link Pulse Minimum Period
Required For Detection
NLP Receive Link Pulse Maximum
Period Required For Detection
NLP Receive Link Pulse Required To
Exit Link Fail State
FLP Transmit Link Pulse Width
FLP Transmit Clock Pulse to Data Pulse
Period
FLP Transmit Clock Pulse to Clock Pulse
Period
FLP Transmit Link Pulse Burst Period
FLP Receive Link Pulse Width Required
For Detection
FLP Receive Link Pulse Minimum Period
Required For Clock Pulse Detection
FLP Receive Link Pulse Maximum
Period Required For Clock Pulse
Detection
FLP Receive Link Pulse Minimum Period
Required For Data Pulse Detection
FLP Receive Link Pulse Maximum
Period Required For Data Pulse
Detection
FLP Receive Link Pulse Burst Minimum
Period Required For Detection
FLP Receive Link Pulse Burst Maximum
Period Required For Detection
FLP Receive Link Pulses Bursts
Required To Detect AutoNegotiation
Capability
Table 14.4 Link Pulse Timing Characteristics
DATASHEET
LIMIT
MIN
See
8
50
6
50
3
100
55.5
111
8
50
5
165
15
78
5
50
3
123
Figure 7.8
TYP
3
62.5
125
3
MAX
24
7
150
3
150
69.5
139
22
25
185
47
100
7
150
3
UNIT
nS
mS
nS
mS
mS
Link
Pulses
nS
μS
μS
mS
nS
μS
μS
μS
μS
mS
mS
Link
Pulses
CONDITIONS
link_test_min
link_test_max
lc_max
interval_timer
transmit_link_burst_time
r
flp_test_min_timer
flp_test_max_timer
data_detect_min_timer
data_detect_max_timer
nlp_test_min_timer
nlp_test_max_timer
Revision 1.91 (06-01-09)

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