LAN91C111I-NS SMSC, LAN91C111I-NS Datasheet - Page 76

IC ETHERNET CTLR MAC PHY 128-QFP

LAN91C111I-NS

Manufacturer Part Number
LAN91C111I-NS
Description
IC ETHERNET CTLR MAC PHY 128-QFP
Manufacturer
SMSC
Type
Single Chip MAC and PHYr
Datasheet

Specifications of LAN91C111I-NS

Controller Type
Ethernet Controller, MAC/PHY
Interface
Serial EEPROM
Voltage - Supply
3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
128-QFP
Product
Ethernet Controllers
Number Of Transceivers
1
Standard Supported
IEEE 802.3 or IEEE 802.3u
Data Rate
10 Mbps or 100 Mbps
Supply Voltage (max)
5 V
Supply Voltage (min)
0 V
Supply Current (max)
140 mA
Maximum Operating Temperature
+ 85 C
Ethernet Connection Type
100BASE-T or 100BASE-T4 or 100BASE-TX or 10BASE-T
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
638-1014

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LAN91C111I-NS
Manufacturer:
RECOM
Quantity:
1 000
Part Number:
LAN91C111I-NS
Manufacturer:
SMSC
Quantity:
1 000
Part Number:
LAN91C111I-NS
Manufacturer:
Standard
Quantity:
6 916
Part Number:
LAN91C111I-NS
Manufacturer:
Microchip Technology
Quantity:
10 000
Revision 1.91 (06-01-09)
9.3
9.4
REG
TX_HDX
2
3
3
3
RW
RW
NP
0
1
15-10
BITS
15-0
Register 2&3. PHY Identifier Register
Register 4. Auto-Negotiation Advertisement Register
9-4
3-0
REM_FLT- Remote Fault Detect
‘1’ indicates a Remote Fault. Latches the ‘1’ condition and is cleared by reading this register or
resetting the PHY.
CAP_ANEG - AutoNegotiation Capable
Indicates the ability (‘1’) to perform ANEG or not (‘0’).
LINK - Link Status
A ‘1’ indicates a valid Link and a ‘0’ and invalid Link. The ‘0’ condition is latched until this register is
read.
JAB - Jabber Detect
Jabber condition detected when ‘1’ for 10Mbps. ‘1’ latched until this register is read or the PHY is reset.
Always ‘0’ for 100Mbps
EXREG - Extended Capability register
These two registers (offsets 2 and 3) provide a 32-bit value unique to the PHY.
This register control the values transmitted by the PHY to the remote partner when advertising its
abilities
‘1’ Indicates extended registers are implemented
10_FDX
ACK
RW
R
1
0
Manufacturer's Revision #
Manufacturer's ID
Company ID
Company ID
NAME
10_HDX
RW
RW
RF
0
1
DATASHEET
Reserved
Reserved
RW
RW
0
0
0000000000010110
DEFAULT VALUE
76
000100
111110
- - - -
Reserved
Reserved
RW
RW
0
0
10/100 Non-PCI Ethernet Single Chip MAC + PHY
Reserved
Reserved
RW
RW
0
0
R/W
R
R
R
R
Retains Original Value
Retains Original Value
Retains Original Value
Retains Original Value
Reserved
SMSC LAN91C111 REV C
RW
RW
T4
SOFT RESET
0
0
TX_FDX
CSMA
Datasheet
RW
RW
1
1

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