LAN91C111I-NS SMSC, LAN91C111I-NS Datasheet - Page 48

• Manufacturer Part Number: LAN91C111I-NS
• Description: IC ETHERNET CTLR MAC PHY 128-QFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN91C111I-NS

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-QFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 140 mA
• Maximum Operating Temperature: + 85 C
• Ethernet Connection Type: 100BASE-T or 100BASE-T4 or 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1014

Revision 1.91 (06-01-09)
8.6
BYTE
BYTE
HIGH
LOW
Bank 0 - EPH Status Register
FORCOL - When set, the FORCOL bit will force a collision by not deferring deliberately. This bit is set
and cleared only by the CPU. When TXENA is enabled with no packets in the queue and while the
FORCOL bit is set, the LAN91C111 will transmit a preamble pattern the next time a carrier is seen on
the line. If a packet is queued, a preamble and SFD will be transmitted. This bit defaults low to normal
operation. NOTE: The LATCOL bit in the EPHSR, setting up as a result of FORCOL, will reset TXENA
to 0. In order to force another collision, TXENA must be set to 1 again.
LOOP - Loopback. General purpose output port used to control the LBK pin. Typically used to put the
PHY chip in loopback mode.
TXENA - Transmit enabled when set. Transmit is disabled if clear. When the bit is cleared the
LAN91C111 will complete the current transmission before stopping. When stopping due to an error,
this bit is automatically cleared.
This register stores the status of the last transmitted frame. This register value, upon individual
transmit packet completion, is stored as the first word in the memory area allocated to the packet.
Packet interrupt processing should use the copy in memory as the register itself will be updated by
subsequent packet transmissions. The register can be used for real time values (like TXENA and LINK
OK). If TXENA is cleared the register holds the last packet completion status.
LINK_OK - General purpose input port driven by nLNK pin inverted. Typically used for Link Test. A
transition on the value of this bit generates an interrupt.
CTR_ROL - Counter Roll Over. When set one or more 4 bit counters have reached maximum count
(15). Cleared by reading the ECR register.
EXC_DEF - Excessive Deferral. When set last/current transmit was deferred for more than 1518 * 2
byte times. Cleared at the end of every packet sent.
LOST_CARR - Lost Carrier Sense. When set indicates that Carrier Sense was not present at end of
preamble. Valid only if MON_CSN is enabled. This condition causes TXENA bit in TCR to be reset.
Cleared by setting TXENA bit in TCR.
LATCOL - Late collision detected on last transmit frame. If set a late collision was detected (later than
64 byte times into the frame). When detected the transmitter jams and turns itself off clearing the
TXENA bit in TCR. Cleared by setting TXENA in TCR.
TX_DEFR - Transmit Deferred. When set, carrier was detected during the first 6.4 μs of the inter frame
gap. Cleared at the end of every packet sent.
LTX_BRD - Last transmit frame was a broadcast. Set if frame was broadcast. Cleared at the start of
every transmit frame.
Reserved
DEFR
TX
0
0
OFFSET
2
-nLNK pin
LINK_
BRD
LTX
OK
0
EPH STATUS REGISTER
Reserved
NAME
SQET
0
0
DATASHEET
16COL
_ROL
CTR
48
0
0
READ ONLY
MULT
_DEF
TYPE
EXC
LTX
0
0
10/100 Non-PCI Ethernet Single Chip MAC + PHY
CARR
LOST
MUL
COL
0
0
SYMBOL
EPHSR
LATCOL
SMSC LAN91C111 REV C
SNGL
COL
0
0
Reserved
TX_SUC
Datasheet
0
0