LAN91C111I-NS SMSC, LAN91C111I-NS Datasheet - Page 98

• Manufacturer Part Number: LAN91C111I-NS
• Description: IC ETHERNET CTLR MAC PHY 128-QFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN91C111I-NS

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-QFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 140 mA
• Maximum Operating Temperature: + 85 C
• Ethernet Connection Type: 100BASE-T or 100BASE-T4 or 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1014

Chapter 12 Application Considerations
Revision 1.91 (06-01-09)
VL BUS
SIGNAL
A2-A15
M/nIO
W/nR
nRDYRTN
nLRDY
LCLK
nRESET
nBE0 nBE1
nBE2 nBE3
nADS
IRQn
The LAN91C111 is envisioned to fit a few different bus types. This section describes the basic
guidelines, system level implications and sample configurations for the most relevant bus types. All
applications are based on buffered architectures with a private SRAM bus.
FAST ETHERNET SLAVE ADAPTER
Slave non-intelligent board implementing 100 Mbps and 10 Mbps speeds.
Adapter requires:
1. LAN91C111 chip
2. Serial EEPROM (93C46)
3. Some bus specific glue logic
Target systems:
1. VL Local Bus 32 bit systems
2. High-end ISA or non-burst EISA machines
3. EISA 32 bit slave
VL Local Bus 32 Bit Systems
On VL Local Bus and other 32 bit embedded systems the LAN91C111 is accessed as a 32 bit
peripheral in terms of the bus interface. All registers except the DATA REGISTER will be accessed
using byte or word instructions. Accesses to the DATA REGISTER could use byte, word, or dword
instructions.
LAN91C111
SIGNAL
A2-A15
AEN
W/nR
nRDYRTN
nSRDY and some
logic
LCLK
RESET
nBE0 nBE1 nBE2
nBE3
nADS, nCYCLE
INTR0
Table 12.1 VL Local Bus Signal Connections
NOTES
Address bus used for I/O space and register decoding, latched by nADS
rising edge, and transparent on nADS low time.
Qualifies valid I/O decoding - enabled access when low. This signal is
latched by nADS rising edge and transparent on nADS low time.
Direction of access. Sampled by the LAN91C111 on first rising clock that
has nCYCLE active. High on writes, low on reads.
Ready return. Direct connection to VL bus.
nSRDY has the appropriate functionality and timing to create the VL
nLRDY except that nLRDY behaves like an open drain output most of
the time.
Local Bus Clock. Rising edges used for synchronous bus interface
transactions.
Connected via inverter to the LAN91C111.
Byte enables. Latched transparently by nADS rising edge.
Address Strobe is connected directly to the VL bus. nCYCLE is created
typically by using nADS delayed by one LCLK.
Typically uses the interrupt lines on the ISA edge connector of VL bus
DATASHEET
98
10/100 Non-PCI Ethernet Single Chip MAC + PHY
SMSC LAN91C111 REV C
Datasheet