LAN91C111I-NS SMSC, LAN91C111I-NS Datasheet - Page 18

• Manufacturer Part Number: LAN91C111I-NS
• Description: IC ETHERNET CTLR MAC PHY 128-QFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN91C111I-NS

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-QFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 140 mA
• Maximum Operating Temperature: + 85 C
• Ethernet Connection Type: 100BASE-T or 100BASE-T4 or 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1014

Revision 1.91 (06-01-09)
PIN NO.
TQFP
125
112
113-116
109
118
121-124
25
26
27
126
2
12
14
15
17
18
22
23
Note 5.1
QFP
127
114
115-118
111
120
123-126
27
28
29
128
4
14
16
17
19
20
24
25
If the EEPROM is enabled.
NAME
Receive Data
Valid
Collision Detect
100 Mbps
Transmit Data
Transmit Clock
Receive Clock
Receive Data
Management
Data Input
Management
Data Output
Management
Clock
Receive Error
nChip Select
Output
External
Resistor
RX25
RX_ER
SYMBOL
RX_DV
COL100
TXD3-
TXD0
TX25
RXD3-
RXD0
MDI
MDO
MCLK
nCSOUT
RBIAS
TPO+
TPO-
TPI+
TPI-
nLEDA
nLEDB
DATASHEET
18
BUFFER
TYPE
I with
pulldown
I with
pulldown
O12
I with
pullup
I with
pullup
I with
pullup
I with
pulldown
O4
O4
I with
pulldown
O4
NA
O/I
O/I
I/O
I/O
OD24
OD24
10/100 Non-PCI Ethernet Single Chip MAC + PHY
DESCRIPTION
Input from MII PHY. Envelope of data
valid reception. Used for receive data
framing.
Input from MII PHY. Collision detection
input.
Outputs. Transmit Data nibble to MII
PHY.
Input. Transmit clock input from MII.
Nibble rate clock (25MHz for 100Mbps &
2.5MHz for 10Mbps).
Input. Receive clock input from MII PHY.
Nibble rate clock. (25MHz for 100Mbps &
2.5MHz for 10Mbps).
Inputs. Received Data nibble from MII
PHY.
MII management data input.
MII management data output.
MII management clock.
Input. Indicates a code error detected by
PHY. Used by the LAN91C111 to discard
the packet being received. The error
indication reported for this event is the
same as a bad CRC (Receive Status
Word bit 13).
Output. Chip Select provided for
mapping of PHY functions into
LAN91C111 decoded space. Active on
accesses to LAN91C111’s eight lower
addresses when the BANK SELECTED is
7.
Transmit Current Set. An external
resistor connected between this pin and
GND will set the output current for the TP
transmit outputs
Twisted Pair Transmit Output, Positive.
Twisted Pair Transmit Output, Negative
Twisted Pair Receive Input, Positive
Twisted Pair Receive Input, Negative.
PHY LED Output
PHY LED Output
SMSC LAN91C111 REV C
Datasheet