LAN91C111I-NS SMSC, LAN91C111I-NS Datasheet - Page 62

• Manufacturer Part Number: LAN91C111I-NS
• Description: IC ETHERNET CTLR MAC PHY 128-QFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN91C111I-NS

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-QFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 140 mA
• Maximum Operating Temperature: + 85 C
• Ethernet Connection Type: 100BASE-T or 100BASE-T4 or 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1014

Revision 1.91 (06-01-09)
8.20
8.21
MDINT
X
X
0
Bank 2 - Data Register
Bank 2 - Interrupt Status Registers
DATA REGISTER - Used to read or write the data buffer byte/word presently addressed by the pointer
register.
This register is mapped into two uni-directional FIFOs that allow moving words to and from the
LAN91C111 regardless of whether the pointer address is even, odd or dword aligned. Data goes
through the write FIFO into memory, and is pre-fetched from memory into the read FIFO. If byte
accesses are used, the appropriate (next) byte can be accessed through the Data Low or Data High
registers. The order to and from the FIFO is preserved. Byte, word and dword accesses can be mixed
on the fly in any order.
This register is mapped into two consecutive word locations to facilitate double word move operations
regardless of the actual bus width (16 or 32 bits). The DATA register is accessible at any address in
the 8 through Bh range, while the number of bytes being transferred is determined by A1 and nBE0-
nBE3. The FIFOs are 12 bytes each.
Reserved
8 THROUGH
OFFSET
X
X
0
OFFSET
C
BH
EPH INT
X
X
INTERRUPT STATUS
0
DATA REGISTER
REGISTER
NAME
RX_OVRN
NAME
INT
DATASHEET
X
X
0
DATA HIGH
DATA LOW
62
ALLOC INT
X
X
0
READ ONLY
READ/WRITE
TYPE
TYPE
10/100 Non-PCI Ethernet Single Chip MAC + PHY
TX EMPTY
INT
X
X
1
SYMBOL
SYMBOL
DATA
IST
TX INT
SMSC LAN91C111 REV C
X
X
0
RCV INT
Datasheet
X
X
0