LAN91C111I-NS SMSC, LAN91C111I-NS Datasheet - Page 61

• Manufacturer Part Number: LAN91C111I-NS
• Description: IC ETHERNET CTLR MAC PHY 128-QFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN91C111I-NS

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-QFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 140 mA
• Maximum Operating Temperature: + 85 C
• Ethernet Connection Type: 100BASE-T or 100BASE-T4 or 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1014

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
SMSC LAN91C111 REV C
8.19
BYTE
BYTE
HIGH
LOW
Bank 2 - Pointer Register
TEMPTY - No transmit packets in completion queue. For polling purposes, uses the TX_INT bit in the
Interrupt Status Register.
TX FIFO PACKET NUMBER - Packet number presently at the output of the TX FIFO. Only valid if
TEMPTY is clear. The packet is removed when a TX INT acknowledge is issued.
Note: For software compatibility with future versions, the value read from each FIFO register is
POINTER REGISTER - The value of this register determines the address to be accessed within the
transmit or receive areas. It will auto-increment on accesses to the data register when AUTO INCR.
is set. The increment is by one for every byte access, by two for every word access, and by four for
every double word access. When RCV is set the address refers to the receive area and uses the
output of RX FIFO as the packet number, when RCV is clear the address refers to the transmit area
and uses the packet number at the Packet Number Register.
READ - Determines the type of access to follow. If the READ bit is high the operation intended is a
read. If the READ bit is low the operation is a write. Loading a new pointer value, with the READ bit
high, generates a pre-fetch into the Data Register for read purposes.
Readback of the pointer will indicate the value of the address last accessed by the CPU (rather than
the last pre-fetched). This allows any interrupt routine that uses the pointer, to save it and restore it
without affecting the process being interrupted. The Pointer Register should not be loaded until the
Data Register FIFO is empty. The NOT EMPTY bit of this register can be read to determine if the
FIFO is empty. On reads, if ARDY is not connected to the host, the Data Register should not be read
before 370ns after the pointer was loaded to allow the Data Register FIFO to fill.
If the pointer is loaded using 8 bit writes, the low byte should be loaded first and the high byte last.
Reserved - Must be 0
NOT EMPTY - When set indicates that the Write Data FIFO is not empty yet. The CPU can verify that
the FIFO is empty before loading a new pointer value. This is a read only bit.
Note: If AUTO INCR. is not set, the pointer must be loaded with a dword aligned value.
RCV
0
0
OFFSET
intended to be written into the PNR as is, without masking higher bits (provided TEMPTY and
REMPTY = 0 respectively).
6
AUTO
INCR.
0
0
POINTER REGISTER
READ
NAME
0
0
DATASHEET
Reserved
POINTER LOW
61
0
0
NOT EMPTY IS
A READ ONLY
READ/WRITE
EMPTY
TYPE
NOT
BIT
0
0
0
0
SYMBOL
PTR
POINTER HIGH
Revision 1.91 (06-01-09)
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