LAN91C111I-NS SMSC, LAN91C111I-NS Datasheet - Page 64

• Manufacturer Part Number: LAN91C111I-NS
• Description: IC ETHERNET CTLR MAC PHY 128-QFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN91C111I-NS

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-QFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 140 mA
• Maximum Operating Temperature: + 85 C
• Ethernet Connection Type: 100BASE-T or 100BASE-T4 or 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1014

Revision 1.91 (06-01-09)
Any of the above interrupt sources can be masked by the appropriate ENABLE bits in the Control
Register.
1. 1) LE ENABLE (Link Error Enable), 2) CR ENABLE (Counter Roll Over), 3) TE ENABLE (Transmit
EPH INT will only be cleared by the following methods:
RX_OVRN INT - Set when 1) the receiver aborts due to an overrun due to a failed memory allocation,
2) the receiver aborts due to a packet length of greater than 2K bytes, or 3) the receiver aborts due
to the RCV DISCRD bit in the RCV register set. The RX_OVRN INT bit latches the condition for the
purpose of being polled or generating an interrupt, and will only be cleared by writing the acknowledge
register with the RX_OVRN INT bit set.
ALLOC INT - Set when an MMU request for TX ram pages is successful. This bit is the complement
of the FAILED bit in the ALLOCATION RESULT register. The ALLOC INT bit is cleared by the MMU
when the next allocation request is processed or allocation fails.
TX EMPTY INT - Set if the TX FIFO goes empty, can be used to generate a single interrupt at the
end of a sequence of packets enqueued for transmission. This bit latches the empty condition, and
the bit will stay set until it is specifically cleared by writing the acknowledge register with the TX EMPTY
INT bit set. If a real time reading of the FIFO empty is desired, the bit should be first cleared and then
read.
The TX_EMPTY MASK bit should only be set after the following steps:
TX INT - Set when at least one packet transmission was completed or any of the below transmit fatal
errors occurs:
The first packet number to be serviced can be read from the FIFO PORTS register. The TX INT bit is
always the logic complement of the TEMPTY bit in the FIFO PORTS register. After servicing a packet
number, its TX INT interrupt is removed by writing the Interrupt Acknowledge Register with the TX INT
bit set.
RCV INT - Set when a receive interrupt is generated. The first packet number to be serviced can be
read from the FIFO PORTS register. The RCV INT bit is always the logic complement of the REMPTY
bit in the FIFO PORTS register.
Receive Interrupt is cleared when RX FIFO is empty.
LATCOL - Late Collision
16COL - 16 collisions
Clearing the LE ENABLE bit in the Control Register if an EPH interrupt is caused by a LINK_OK
transition.
Reading the Counter Register if an EPH interrupt is caused by statistics counter roll over.
Setting TXENA bit high if an EPH interrupt is caused by any of the fatal transmit error listed above
(3.1 to 3.5).
A packet is enqueued for transmission
The previous empty condition is cleared (acknowledged)
SQET - SQE Error
LOST CARR - Lost Carrier
LATCOL - Late Collision
16COL - 16 collisions
Error Enable)
DATASHEET
64
10/100 Non-PCI Ethernet Single Chip MAC + PHY
SMSC LAN91C111 REV C
Datasheet