LAN91C111I-NS SMSC, LAN91C111I-NS Datasheet - Page 51

• Manufacturer Part Number: LAN91C111I-NS
• Description: IC ETHERNET CTLR MAC PHY 128-QFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN91C111I-NS

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-QFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 140 mA
• Maximum Operating Temperature: + 85 C
• Ethernet Connection Type: 100BASE-T or 100BASE-T4 or 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1014

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
SMSC LAN91C111 REV C
8.9
8.10
BYTE
BYTE
BYTE
BYTE
HIGH
HIGH
LOW
LOW
Bank 0 - Memory Information Register
Bank 0 - Receive/Phy Control Register
FREE MEMORY AVAILABLE - This register can be read at any time to determine the amount of free
memory. The register defaults to the MEMORY SIZE upon POR (Power On Reset) or upon the RESET
MMU command.
MEMORY SIZE - This register can be read to determine the total memory size.
All memory related information is represented in 2K * M byte units, where the multiplier M is 1 for
LAN91C111.
SPEED – Speed select Input. This bit is valid and selects 10/100 PHY operation only when the ANEG
Bit = 0, this bit overrides the SPEED bit in the PHY Register 0 (Control Register) and determine the
speed mode. When this bit is set (1), the Internal PHY will operate at 100Mbps. When this bit is
cleared (0), the Internal PHY will operate at 10Mbps. When the ANEG bit = 1, this bit is ignored and
10/100 operation is determined by the outcome of the Auto-negotiation or this bit is overridden by the
SPEED bit in the PHY Register 0 (Control Register) when the ANEG_EN bit in the PHY Register 0
(Control Register) is clear.
DPLX – Duplex Select - This bit selects Full/Half Duplex operation. This bit is valid and selects duplex
operation only when the ANEG Bit = 0, this bit overrides the DPLX bit in the PHY Register 0 (Control
Reserved
LS2A
0
0
0
0
OFFSET
OFFSET
A
8
Reserved
LS1A
0
0
0
0
RECEIVE/PHY CONTROL
MEMORY INFORMATION
FREE MEMORY AVAILABLE (IN BYTES * 2K * M)
REGISTER
REGISTER
SPEED
NAME
NAME
LS0A
0
0
0
0
MEMORY SIZE (IN BYTES *2K * M)
DATASHEET
DPLX
LS2B
0
0
51
0
0
READ/WRITE
READ ONLY
ANEG
LS1B
TYPE
TYPE
0
0
0
0
Reserved
LS0B
0
0
1
1
SYMBOL
SYMBOL
RPCR
MIR
Reserved
Reserved
Revision 1.91 (06-01-09)
0
0
0
0
Reserved
Reserved
0
0
0
0