LAN91C111I-NS SMSC, LAN91C111I-NS Datasheet - Page 52

• Manufacturer Part Number: LAN91C111I-NS
• Description: IC ETHERNET CTLR MAC PHY 128-QFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN91C111I-NS

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-QFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 140 mA
• Maximum Operating Temperature: + 85 C
• Ethernet Connection Type: 100BASE-T or 100BASE-T4 or 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1014

Try to Manually Set to
Revision 1.91 (06-01-09)
Try to Auto-Negotiate
WHAT DO YOU
WANT TO DO?
100 Half Duplex
100 Full Duplex
WHAT DO YOU
WANT TO DO?
100 Half Duplex
100 Full Duplex
10 Half Duplex
10 Full Duplex
to ……
……
Register) and determine the duplex mode. When this bit is set (1), the Internal PHY will operate at
full duplex mode. When this bit is cleared (0), the Internal PHY will operate at half Duplex mode. When
the ANEG bit = 1, this bit is ignored and duplex mode is determined by the outcome of the Auto-
negotiation or this bit is overridden by the DPLX bit in the PHY Register 0 (Control Register) when the
ANEG_EN bit in the PHY Register 0 (Control Register) is clear.
ANEG – Auto-Negotiation mode select - The PHY is placed in Auto-Negotiation mode when the ANEG
bit and the ANEG_EN bit in PHY Register 0 (Control Register) both are set. When either of these bits
is cleared (0), the PHY is placed in manual mode.
AUTO-NEGOTIATION
Offset A)
Bank 0
ANEG
RPCR
(MAC)
ANEG
RPCR
(MAC
CONTROL BITS
CONTROL BITS
Bit
Bit
NEGOTIATION
1
1
1
1
0
0
1
0
0
1
AUTO-
Register 0
Register 0
ANEG_E
ANEG_E
(PHY)
(PHY)
Bit
N
Bit
1
1
1
1
N
0
1
0
0
1
0
DATASHEET
TX_FDX
Register
Offset A)
SPEED
(PHY)
Bank 0
RPCR
AUTO-NEGOTIATION ADVERTISEMENT
(MAC
SPEED AND DUPLEX MODE CONTROL
Bit
Bit
4
1
0
0
0
1
X
1
X
1
1
52
TX_HDX
Register
Offset A)
(PHY)
Bank 0
RPCR
DPLX
(MAC
Bit
FOR THE PHY
Bit
4
1
1
0
0
X
X
1
1
0
0
REGISTER
10/100 Non-PCI Ethernet Single Chip MAC + PHY
10_FDX
Register
Register
SPEED
(PHY)
(PHY)
Bit
Bit
4
1
1
1
0
X
X
X
X
0
1
1
10_HDX
Register
Register
(PHY)
(PHY)
DPLX
Bit
Bit
4
1
1
1
1
SMSC LAN91C111 REV C
X
X
X
X
0
1
0
CONTROL
FOR THE
CONTROL
SWFDUP
DUPLEX
FOR THE
Transmit
SWFDUP
Register
DUPLEX
Transmit
Control
Register
MODE
(MAC)
Control
MODE
(MAC)
MAC
MAC
Datasheet
Bit
Bit
1
0
1
0
1
1
1
0
0
0