LAN91C111I-NS SMSC, LAN91C111I-NS Datasheet - Page 40

• Manufacturer Part Number: LAN91C111I-NS
• Description: IC ETHERNET CTLR MAC PHY 128-QFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN91C111I-NS

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-QFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 140 mA
• Maximum Operating Temperature: + 85 C
• Ethernet Connection Type: 100BASE-T or 100BASE-T4 or 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1014

Revision 1.91 (06-01-09)
7.7.13
7.7.14
device halts all transmissions including link pulses for 1200-1500 ms, enters the Link Fail State, and
restarts the negotiation process. When AutoNegotiation mode is turned on or reset, software driver
should wait for at least 1500ms to read the ANEG_ACK bit in the MI PHY Status Register to determine
whether the AutoNegotiation process has been completed. When the ANEG bit in the Receive/PHY
Control Register is cleared, AutoNegotiation algorithm is disabled, the selection of 10/100 Mbps mode
and duplex mode is determined by the SPEED bit and the DPLX bit in the MAC Receive/PHY Control
register. When the ANEG bit in the Receive/PHY Control Register is set and the ANEG_EN bit in the
MI PHY Register 0 (Control Register) is cleared, AutoNegotiation algorithm is disabled, the selection
of 10/100 Mbps mode and duplex mode is determined by the SPEED bit and the DPLX bit in the MI
PHY Register 0 (Control Register).
AutoNegotiation Reset
The AutoNegotiation algorithm can be initiated at any time by setting the AutoNegotiation reset bit in
the PHY MI serial port Control register.
Link Disable
The link integrity function can be disabled by setting the link disable bit in the PHY Ml serial port
Configuration 1 register. When the link integrity function is disabled, the device is forced into the Link
Pass state, configures itself for Half/Full Duplex based on the value of the duplex bit in the PHY MI
serial port Control register, configures itself for 100/10 Mbps operation based on the values of the
speed bit in the Ml serial port Control register, and continues to transmit NLP'S or TX idle patterns,
depending on whether the device is in 10 or 100 Mbps mode.
Jabber
100 Mbps
Jabber function is disabled in the 100 Mbps mode.
10 Mbps
Jabber condition occurs when the transmit packet exceeds a predetermined length. When jabber is
detected, the TP transmit outputs are forced to the idle state, collision is asserted, and register bits in
the PHY Ml serial port Status and Status Output registers are set.
Jabber Disable
The jabber function can be disabled by setting the jabber disable bit in the PHY MI serial port
Configuration 2 register.
Receive Polarity Correction
100 Mbps
No polarity detection or correction is needed in 100Mbps mode.
10 Mbps
The polarity of the signal on the TP receive input is continuously monitored. If either 3 consecutive
link pulses or one SOI pulse indicates incorrect polarity on the TP receive input, the polarity is internally
determined to be incorrect, and a reverse polarity bit is set in the PHY Ml serial port Status Output
register.
The LAN91C111 will automatically correct for the reverse polarity condition provided that the
autopolarity feature is not disabled.
Note: The first 3 received packets must be discarded after the correction of a reverse polarity
condition.
DATASHEET
40
10/100 Non-PCI Ethernet Single Chip MAC + PHY
SMSC LAN91C111 REV C
Datasheet