LAN91C111I-NS SMSC, LAN91C111I-NS Datasheet - Page 128

• Manufacturer Part Number: LAN91C111I-NS
• Description: IC ETHERNET CTLR MAC PHY 128-QFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN91C111I-NS

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-QFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 140 mA
• Maximum Operating Temperature: + 85 C
• Ethernet Connection Type: 100BASE-T or 100BASE-T4 or 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1014

Chapter 16 Revision History
Revision 1.91 (06-01-09)
REVISION LEVEL & DATE
(06-01-09)
(07-17-08)
(07-17-08)
(07-17-08)
(07-17-08)
(07-17-08)
(07-17-08)
(07-17-08)
Rev. 1.91
Rev. 1.9
Rev. 1.9
Rev. 1.9
Rev. 1.9
Rev. 1.9
Rev. 1.9
Rev. 1.9
All
Section 13.1, "Maximum
Guaranteed Ratings*," on
page 105
Cover
Section 8.24, "Bank 3 -
Revision Register," on
page 67
Table 14.3, “Asynchronous
Cycle - nADS=0,” on
page 112
Section 10.4, "Typical Flow
of Event For Receive," on
page 87
Section 7.7.14, "Receive
Polarity Correction," on
page 40
SECTION/FIGURE/ENTRY
Table 16.1 Customer Revision History
DATASHEET
128
The following ordering information has been
removed: “LAN91C111-NC, LAN91C111i-NC
(Industrial Temperature) for 128 pin QFP
packages”, “LAN91C111-NE, LAN91C111i-NE
(Industrial Temperature) for 128-pin TQFP
packages” as these has been discontinued.
Updated document references to Rev. C.
Fixed commercial temp range to state “0°C to
+70°C for LAN91C111”
Added bullet: “Commercial Temperature Range
from 0°C to 70°C (LAN91C111)”
Changed REV default from “0001” to “0010”
Changed T1A time in table under figure from 10nS
min to 2nS min.
In step 4, changed last sentence from “If CRC is
incorrect the packet memory is released and no
interrupt will occur.”, to “The RCV_BAD bit of the
Bank 1 Control Register controls whether or not to
generate interrupts when bad CRC packets are
received.”
Added note at end of 10 Mbps subsection stating
“The first 3 received packets must be discarded
after the correction of a reverse polarity condition.”
10/100 Non-PCI Ethernet Single Chip MAC + PHY
CORRECTION
SMSC LAN91C111 REV C
Datasheet