LAN91C111I-NS SMSC, LAN91C111I-NS Datasheet - Page 24

• Manufacturer Part Number: LAN91C111I-NS
• Description: IC ETHERNET CTLR MAC PHY 128-QFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN91C111I-NS

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-QFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 140 mA
• Maximum Operating Temperature: + 85 C
• Ethernet Connection Type: 100BASE-T or 100BASE-T4 or 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1014

Revision 1.91 (06-01-09)
7.5.4
TX_EN = 0
MII
NIBBLE
STREAM
IDLE
MII Packet Data Communication with External PHY
The MIl is a nibble wide packet data interface defined in IEEE 802.3. The LAN91C111 meets all the
MIl requirements outlined in IEEE 802.3 and shown in
The Mll consists of the following signals: four transmit data bits (TXD[3:0]), transmit clock
(TX25),transmit enable (TXEN100), four receive data bits(RXD[3:0]), receive clock(RX25), carrier
sense (CRS100), receive data valid (RX_DV), receive data error (RX_ER), and collision (COL100).
Transmit data is clocked out using the TX25 clock input, while receive data is clocked in using RX25. The
transmit and receive clocks operate at 25 MHz in 100Mbps mode and 2.5 MHz in 10Mbps.
In 100 Mbps mode, the LAN91C111 provides the following interface signals to the PHY:
A transmission begins by TXEN100 going active (high), and TXD0-TXD3 having the first valid
preamble nibble. TXD0 carries the least significant bit of the nibble (that is the one that would go first
out of the EPH at 100 Mbps), while TXD3 carries the most significant bit of the nibble. TXEN100 and
TXD0-TXD3 are clocked by the LAN91C111 using TX25 rising edges. TXEN100 goes inactive at the
end of the packet on the last nibble of the CRC.
During a transmission, COL100 might become active to indicate a collision. COL100 is asynchronous
to the LAN91C111’s clocks and will be synchronized internally to TX25.
Reception begins when RX_DV (receive data valid) is asserted. A preamble pattern or flag octet will
be present at RXD0-RXD3 when RX_DV is activated. The LAN91C111 requires no training sequence
beyond a full flag octet for reception. RX_DV as well as RXD0-RXD3 are sampled on RX25 rising
For transmission: TXEN100, TXD0-3, TX25
For reception: RX_DV, RX_ER, RXD0-3, RX25
For CSMA/CD state machines: CRS100, COL100
TXD0 / RXD0
TXD1 / RXD1
TXD2 / RXD2
TXD3 / RXD3
FIRST BIT
FIRST
NIBBLE
PREAMBLE
PRMBLE
62 BT
LSB
Figure 7.2 MII Frame Format & MII Nibble Order
PREAMBLE
D0
DATAn
START
FRAME
DELIM.
SFD
IDLE = TX_EN = 0
D1
2 BT
SFD
OF
= [ 1 0 1 0 ... ] 62 BITS LONG
= [ 1 1 ]
= [ BETWEEN 64-1518 DATA BYTES ]
DATASHEET
MAC's SERIAL BIT STREAM
D2
TX_EN = 1
DATA 1
D3
24
D4
DATA 2
DATA NIBBLES
D5
Figure
10/100 Non-PCI Ethernet Single Chip MAC + PHY
D6
7.2.
DATA N-1
D7
MSB
DATA N
SECOND
NIBBLE
SMSC LAN91C111 REV C
TX_EN = 0
IDLE
Datasheet