LAN91C111I-NS SMSC, LAN91C111I-NS Datasheet - Page 46

• Manufacturer Part Number: LAN91C111I-NS
• Description: IC ETHERNET CTLR MAC PHY 128-QFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN91C111I-NS

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-QFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 140 mA
• Maximum Operating Temperature: + 85 C
• Ethernet Connection Type: 100BASE-T or 100BASE-T4 or 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1014

Revision 1.91 (06-01-09)
8.4
C
0
2
4
6
8
A
E
BYTE
BYTE
HIGH
LOW
Bank Select Register
EPH STATUS
RESERVED
COUNTER
Regardless of the functional description, all registers can be accessed as doublewords, words or bytes.
The default bit values upon hard reset are highlighted below each register.
A special BANK (BANK7) exists to support the addition of external registers.
BS2, BS1, BS0 Determine the bank presently in use. This register is always accessible and is used
to select the register bank in use.
The upper byte always reads as 33h and can be used to help determine the I/O location of the
LAN91C111.
The BANK SELECT REGISTER is always accessible regardless of the value of BS0-2
Note: The bank select register can be accessed as a doubleword at offset 0x0Ch, as a word at offset
BANK 7 has no internal registers other than the BANK SELECT REGISTER itself. On valid cycles
where BANK7 is selected (BS0=BS1=BS2=1), and A3=0, nCSOUT is activated to facilitate
implementation of external registers.
Note: BANK7 does not exist in LAN91C9x devices. For backward S/W compatibility BANK7 accesses
Reserved
BANK0
RPCR
BANK
RCR
TCR
MIR
0
X
OFFSET
0x0Eh, or as a byte at offset 0x0Eh, A doubleword write to offset 0x0Ch will write the BANK
SELECT REGISTER but will not write the registers 0x0Ch and 0x0Dh, but will only write to
register 0x0Eh
should be done if the Revision Control register indicates the device is the LAN91C111.
E
Reserved
X
0
BANK SELECT REGISTER
GENERAL PURPOSE
Table 8.1 Internal I/O Space Mapping
Reserved
CONTROL
NAME
CONFIG
BANK1
BANK
X
BASE
1
IA0-1
IA2-3
IA4-5
DATASHEET
Reserved
46
X
1
READ/WRITE
Reserved
TYPE
MMU COMMAND
0
X
FIFO PORTS
INTERRUPT
10/100 Non-PCI Ethernet Single Chip MAC + PHY
POINTER
BANK2
BANK
DATA
DATA
PNR
Reserved
BS2
0
0
SYMBOL
BSR
Reserved
SMSC LAN91C111 REV C
BS1
1
0
REVISION
BANK3
MGMT
MT0-1
MT2-3
MT4-5
MT6-7
BANK
RCV
Reserved
Datasheet
BS0
1
0