LAN91C111I-NS SMSC, LAN91C111I-NS Datasheet - Page 90

• Manufacturer Part Number: LAN91C111I-NS
• Description: IC ETHERNET CTLR MAC PHY 128-QFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN91C111I-NS

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-QFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 140 mA
• Maximum Operating Temperature: + 85 C
• Ethernet Connection Type: 100BASE-T or 100BASE-T4 or 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1014

Revision 1.91 (06-01-09)
1. Save the Packet Number Register
2. Read the EPH Status Register
3. Acknowledge TX Interrupt
4. Check for Status of Transmission
5. Restore the Packet Number Register
Saved_PNR = Read Byte (Bank 2, Offset 2)
Temp = Read (Bank 0, Offset 2)
Write Byte (0x02, (Bank 2, Offset C));
If ( Temp AND 0x0001)
{
}
else
{
}
Write Byte (Saved_PNR, (Bank 2, Offset 2))
TX Interrupt With AUTO_RELEASE = FALSE
//If Successful Transmission
Step 4.1.1: Issue MMU Release (Release Specific Packet)
Step 4.1.2: Return from the routine
//Transmission has FAILED
// Now we can either release or re-enqueue the packet
Step 4.2.1: Get the packet to release/re-enqueue, stored in FIFO
Step 4.2.2: Write to the PNR
Step 4.2.3
Step 4.2.4: Re-Enable Transmission
Step 4.2.5: Return from the routine
Write (0x00A0, (Bank2, Offset 0));
Temp = Read (Bank 2, Offset 4)
Temp = Temp & 0x003F
Write (Temp, (Bank2, Offset 2))
// Option 1: Release the packet
//Option 2: Re-Enqueue the packet
Temp = Read(Bank0, Offset 0);
Temp = Temp2 OR 0x0001
Write (Temp2, (Bank 0, Offset 0));
Figure 10.3 TX INTR
DATASHEET
Write (0x00A0, (Bank2, Offset 0));
Write (0x00C0, (Bank2, Offset 0));
90
10/100 Non-PCI Ethernet Single Chip MAC + PHY
SMSC LAN91C111 REV C
Datasheet