LAN91C111I-NS SMSC, LAN91C111I-NS Datasheet - Page 84

• Manufacturer Part Number: LAN91C111I-NS
• Description: IC ETHERNET CTLR MAC PHY 128-QFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN91C111I-NS

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-QFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 140 mA
• Maximum Operating Temperature: + 85 C
• Ethernet Connection Type: 100BASE-T or 100BASE-T4 or 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1014

Chapter 10 Software Driver and Hardware Sequence
Revision 1.91 (06-01-09)
10.1
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S/W DRIVER
Disable Transmitter – Clear the TXENA bit of the
Transmit Control Register
Remove and release all TX completion packet
numbers on the TX completion FIFO.
Disable Receiver – Clear the RXEN bit of the
Receive Control Register.
Process all Received packets and Issue a Remove
and Release command for each respective RX
packet buffer.
Disable Interrupt sources – Clear the Interrupt
Status Register
Save Device Context – Save all Specific Register
Values set by the driver.
Set PDN bit in PHY MI Register 0 to 1
Write to the “EPH Power EN” Bit located in the
configuration register, Bank 1 Offset 0.
The Ethernet MAC is now in low power mode. The
Host may access all Runtime IO mapped registers.
All IO registers are still accessible. However, the
Host should not read or write to the registers with
the exception of:
Configuration Register
Control Register
Bank Register
Software Driver and Hardware Sequence Flow for Power
Management
This section describes the sequence of events and the interaction between the Host Driver and the
Ethernet controller to perform power management. The Ethernet controller has the ability to reduce its
power consumption when the Device is not required to receive or transmit Ethernet Packets.
Power Management is obtained by disabling the EPH clocks, including the Clocks derived from the
Internal PHY block to reduce internal switching, this reducing current consumption.
The Host interface however, will still be accessible. As discussed in
tables describe the interaction between the EPH and Host driver allowing the Device to transition from
low power state to normal functionality and vice versa.
Table 10.1 Typical Flow Of Events For Placing Device In Low Power Mode
Flow
DATASHEET
84
CONTROLLER FUNCTION
Ethernet MAC finishes packet currently being
transmitted.
The receiver completes receiving the current frame, if
any, and then goes idle. Ethernet MAC will no longer
receive any packets.
RX and TX completion FIFO’s are now Empty and
all MMU packet numbers are now free.
The internal PHY entered in powerdown mode, the
TP outputs are in high impedance state.
Ethernet MAC gates the RX Clock, TX clock derived
from the Internal PHY. The EPH Clock is also
disabled.
10/100 Non-PCI Ethernet Single Chip MAC + PHY
Table 10.1
SMSC LAN91C111 REV C
and
Table
Datasheet
10.2, the