LAN91C111I-NS SMSC, LAN91C111I-NS Datasheet - Page 25

• Manufacturer Part Number: LAN91C111I-NS
• Description: IC ETHERNET CTLR MAC PHY 128-QFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN91C111I-NS

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-QFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 140 mA
• Maximum Operating Temperature: + 85 C
• Ethernet Connection Type: 100BASE-T or 100BASE-T4 or 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1014

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
SMSC LAN91C111 REV C
7.6
7.7
Serial EEPROM Interface
Internal Physical Layer
edges. RXD0 carries the least significant bit and RXD3 the most significant bit of the nibble. RX_DV
goes inactive when the last valid nibble of the packet (CRC) is presented at RXD0-RXD3.
RX_ER might be asserted during packet reception to signal the LAN91C111 that the present receive
packet is invalid. The LAN91C111 will discard the packet by treating it as a CRC error.
RXD0-RXD3 should always be aligned to packet nibbles, therefore, opening flag detection does not
consider misaligned cases. Opening flag detection expects the 5Dh pattern and will not reject the
packet on non-preamble patterns.
CRS100 is used as a frame envelope signal for the CSMA/CD MAC state machines (deferral and
backoff functions), but it is not used for receive framing functions. CRS100 is an asynchronous signal
and it will be active whenever there is activity on the cable, including LAN91C111 transmissions and
collisions.
This block is responsible for reading the serial EEPROM upon hardware reset (or equivalent
command) and defining defaults for some key registers. A write operation is also implemented by this
block, that under CPU command will program specific locations in the EEPROM. This block is an
autonomous state machine and controls the internal Data Bus of the LAN91C111 during active
operation.
The LAN91C111 integrates the IEEE 802.3 physical layer (PHY) internally. The EXT PHY bit in the
Configuration Register is 0 as the default configuration to set the internal PHY enabled. The internal
PHY address is 00000, the driver must use this address to talk to the internal PHY. The internal PHY
is placed in isolation mode at power up and reset. It can be removed from isolation mode by clearing
the MII_DIS bit in the PHY Control Register. If necessary, the internal PHY can be enabled by clearing
the EXT_PHY bit in the Configuration Register.
The internal PHY of LAN91C111 has nine main sections: controller interface, encoder, decoder,
scrambler, descrambler, clock and data recovery, twisted pair transmitter, twisted pair receiver, and MI
serial port.
The LAN91C111 can operate as a 100BASE-TX device (hereafter referred to as 100Mbps mode) or
as a 10BASE-T device (hereafter referred to as 10Mbps mode). The difference between the 100Mbps
mode and the 10Mbps mode is data rate, signaling protocol, and allowed wiring. The 100Mbps TX
mode uses two pairs of category 5 or better UTP or STP twisted pair cable with 4B5B encoded,
scrambled, and MLT-3 coded 62.5 MHz ternary data to achieve a throughput of 100Mbps. The 10Mbps
mode uses two pairs of category 3 or better UTP or STP twisted pair cable with Manchester encoded,
10MHz binary data to achieve a 10Mbps throughput. The data symbol format on the twisted pair cable
for the 100 and 10Mbps modes are defined in IEEE 802.3 specifications and shown in
DATASHEET
25
Revision 1.91 (06-01-09)
Figure
7.3.