LAN91C111I-NS SMSC, LAN91C111I-NS Datasheet - Page 26

• Manufacturer Part Number: LAN91C111I-NS
• Description: IC ETHERNET CTLR MAC PHY 128-QFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN91C111I-NS

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-QFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 140 mA
• Maximum Operating Temperature: + 85 C
• Ethernet Connection Type: 100BASE-T or 100BASE-T4 or 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1014

Revision 1.91 (06-01-09)
INTERFRAME
IDLE
IDLE
GAP
On the transmit side for 100Mbps TX operation, data is received on the controller and then sent to the
4B5B encoder for formatting. The encoded data is then sent to the scrambler. The scrambled and
encoded data is then sent to the TP transmitter. The TP transmitter converts the encoded and
scrambled data into MLT-3 ternary format, reshapes the output, and drives the twisted pair cable.
On the receive side for 100Mbps TX operation, the twisted pair receiver receives incoming encoded
and scrambled MLT-3 data from the twisted pair cable, remove any high frequency noise, equalizes
the input signal to compensate for the effects of the cable, qualifies the data with a squelch algorithm,
and converts the data from MLT-3 coded twisted pair levels to internal digital levels. The output of the
twisted pair receiver then goes to a clock and data recovery block which recovers a clock from the
incoming data, uses the clock to latch in valid data into the device, and converts the data back to NRZ
format. The NRZ data is then unscrambled and decoded by the 4B5B decoder and descrambler,
respectively, and outputted to the Ethernet controller.
DA, SA, LN, LLC DATA, FCS
SSD
DA, SA, LN, LLC DATA, FCS
PREAMBLE
PREAMBLE
PREAMBLE
SOI
PREAMBLE
PREAMBLE
IDLE
= [ 1 1 ] WITH NO MID BIT TRANSITION
SFD
Figure 7.3 TX/10BT Frame Format
IDLE
SSD
SFD
ESD
100 BASE-TX DATA SYMBOLS
10 BASE-T DATA SYMBOLS
= [ DATA]
= [ 1 1]
= [ 1 0 1 0 ... ] 62 BITS LONG
= [ NO TRANSITIONS]
SFD
SFD
SFD
= [ 1 0 1 0 ...] 62 BITS LONG
= [ DATA]
= [ 1 1]
= [ 1 1 0 0 0 1 0 0 0 1]
= [ 0 1 1 0 1 0 0 1 1 1]
DATASHEET
ETHERNET MAC
= [ 1 1 1 1...]
FRAME
DA
DA
DA
26
SA
SA
SA
10/100 Non-PCI Ethernet Single Chip MAC + PHY
LN
LN
LN
4B5B ENCODING,
BEFORE / AFTER
SCRAMBLING,
LLC DATA
LLC DATA FCS
BEFORE / AFTER
LLC DATA FCS
AND MLT3
MANCHESTER
CODING
ENCODING
SMSC LAN91C111 REV C
FCS
SOI
ESD
INTERFRAME
Datasheet
GAP
IDLE
IDLE