mc68hc08ln56 Freescale Semiconductor, Inc, mc68hc08ln56 Datasheet - Page 100

• Manufacturer Part Number: mc68hc08ln56
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Timer Interface Module (TIM)
10.3.7 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as described in
Modulation
pulse width value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect
operation for up to two PWM periods. For example, writing a new value before the counter reaches the
old value but after the counter reaches the new value prevents any compare during that PWM period.
Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the
compare to be missed. The TIM may pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x:
10.3.8 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the
PTE0/TCH0 pin. The TIM channel registers of the linked pair alternately control the pulse width of the
output.
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When changing to a shorter pulse width, enable channel x output compare interrupts and write the
new value in the output compare interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the PWM period to write the new
value.
When changing to a longer pulse width, enable channel x TIM overflow interrupts and write the new
value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the
current PWM period. Writing a larger value in an output compare interrupt routine (at the end of the
current pulse) could cause two output compares to occur in the same PWM period.
(PWM). The pulses are unbuffered because changing the pulse width requires writing the new
PTEx/TCHx
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0% duty
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare also can
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
MC68HC08LN56 • MC68HC708LN56 General Release Specification, Rev. 2.1
OVERFLOW
Figure 10-2. PWM Period and Pulse Width
PULSE
WIDTH
PERIOD
COMPARE
OUTPUT
OVERFLOW
NOTE
COMPARE
OUTPUT
OVERFLOW
Freescale Semiconductor
COMPARE
OUTPUT
10.3.6 Pulse Width