mc68hc08ln56 Freescale Semiconductor, Inc, mc68hc08ln56 Datasheet - Page 54

• Manufacturer Part Number: mc68hc08ln56
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Clock Generator Module (CGMB)
4.5.6 PLL Reference Divider Select Register
The PLL reference divider select register contains the programming information for the modulo reference
divider.
RDS[3:0] — Reference Divider Select Bits
PRDS[7:4] — Unimplemented Bits
4.6 Interrupts
When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU
interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL)
enables CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL, becomes set whether
interrupts are enabled or not. When the AUTO bit is clear, CPU interrupts from the PLL are disabled and
PLLF reads as logic zero.
Software should read the LOCK bit after a PLL interrupt request to see if the request was due to an entry
into lock or an exit from lock. When the PLL enters lock, the VCO clock, CGMVCLK, divided by two can
be selected as the CGMOUT source by setting BCS in the PCTL. When the PLL exits lock, the VCO clock
frequency is corrupt, and appropriate precautions should be taken. If the application is not frequency
sensitive, interrupts should be disabled to prevent PLL interrupt service routines from impeding software
performance or from exceeding stack limitations.
4.7 Special Modes
The WAIT instruction puts the MCU in low-power-consumption standby modes.
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These read/write bits control the modulo reference divider that selects the reference division factor R.
(See
bit in the PCTL is set. A value of $00 in the reference divider select register configures the reference
divider the same as a value of $01. (See
register to $01 for a default divide value of 1.
These bits have no function and always read as logic zeros.
4.3.3 PLL Circuits
$004F
PRDS
Reset:
Read:
Write:
The reference divider select bits have built-in protection such that they
cannot be written when the PLL is on (PLLON = 1).
Software can select the CGMVCLK divided by two as the CGMOUT source
even if the PLL is not locked (LOCK = 0). Therefore, software should make
sure the PLL is locked before setting the BCS bit.
MC68HC08LN56 • MC68HC708LN56 General Release Specification, Rev. 2.1
Figure 4-9. PLL Reference Divider Select Register (PRDS)
Bit 7
0
0
and
= Unimplemented
4.3.6 Programming the
6
0
0
5
0
0
4.3.7 Special Programming
NOTE
NOTE
4
0
0
PLL.) RDS[7:0] cannot be written when the PLLON
RDS3
3
0
RDS2
2
0
Exceptions.) Reset initializes the
RDS1
1
0
Freescale Semiconductor
RDS0
Bit 0
1