mc68hc08ln56 Freescale Semiconductor, Inc, mc68hc08ln56 Datasheet - Page 155

• Manufacturer Part Number: mc68hc08ln56
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

TE — Transmitter Enable Bit
RE — Receiver Enable Bit
RWU — Receiver Wake-Up Bit
SBK — Send Break Bit
Freescale Semiconductor
Setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic ones from
the transmit shift register to the PTE5/TxD pin. If software clears the TE bit, the transmitter completes
any transmission in progress before the PTE5/TxD returns to the idle condition (logic one). Clearing
and then setting TE during a transmission queues an idle character to be sent after the character
currently being transmitted. Reset clears the TE bit.
Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver but does not
affect receiver interrupt flag bits. Reset clears the RE bit.
This read/write bit puts the receiver in a standby state during which receiver interrupts are disabled.
The WAKE bit in SCC1 determines whether an idle input or an address mark brings the receiver out
of the standby state and clears the RWU bit. Reset clears the RWU bit.
Setting and then clearing this read/write bit transmits a break character followed by a logic one. The
logic one after the break character guarantees recognition of a valid start bit. If SBK remains set, the
transmitter continuously transmits break characters with no logic ones between them. Reset clears the
SBK bit.
1 = Transmitter enabled
0 = Transmitter disabled
1 = Receiver enabled
0 = Receiver disabled
1 = Standby state
0 = Normal operation
1 = Transmit break characters
0 = No break characters being transmitted
When SCI receiver DMA service requests are enabled (DMARE = 1), then
SCI receiver CPU interrupt requests are disabled, and the state of the ILIE
bit has no effect.
Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is clear.
ENSCI is in SCI control register 1.
Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.
Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling
SBK before the preamble begins causes the SCI to send a break character
instead of a preamble.
MC68HC08LN56 • MC68HC708LN56 General Release Specification, Rev. 2.1
NOTE
NOTE
NOTE
NOTE
I/O Registers
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