mc68hc08ln56 Freescale Semiconductor, Inc, mc68hc08ln56 Datasheet - Page 116

• Manufacturer Part Number: mc68hc08ln56
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Serial Peripheral Interface Module (SPI)
11.4.1 Master Mode
The SPI operates in master mode when the SPI master bit, SPMSTR, is set.
Only a master SPI module can initiate transmissions. Software begins the transmission from a master SPI
module by writing to the transmit data register. If the shift register is empty, the byte immediately transfers
to the shift register, setting the SPI transmitter empty bit, SPTE. The byte begins shifting out on the MOSI
pin under the control of the serial clock. See
The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register.
(See
master also controls the shift register of the slave peripheral.
As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master’s
MISO pin. The transmission ends when the receiver full bit, SPRF, becomes set. At the same time that
SPRF becomes set, the byte from the slave transfers to the receive data register. In normal operation,
SPRF signals the end of a transmission. Software clears SPRF by reading the SPI status and control
register with SPRF set and then reading the SPI data register. Writing to the SPI data register clears the
SPTE bit.
When the DMAS bit is set, the SPI status and control register does not have to be read to clear the SPRF
bit. A read of the SPI data register by either the CPU or the DMA clears the SPRF bit. A write to the SPI
data register by the CPU or by the DMA clears the SPTE bit.
11.4.2 Slave Mode
The SPI operates in slave mode when the SPMSTR bit is clear. In slave mode the SPSCK pin is the input
for the serial clock from the master MCU. Before a data transmission occurs, the SS pin of the slave SPI
must be at logic zero. SS must remain low until the transmission is complete. (See
Error.)
In a slave SPI module, data enters the shift register under the control of the serial clock from the master
SPI module. After a byte enters the shift register of a slave SPI, it transfers to the receive data register,
and the SPRF bit is set. To prevent an overflow condition, slave software then must read the receive data
register before another full byte enters the shift register.
116
11.13.2 SPI Status and Control
Configure the SPI modules as master or slave before enabling them.
Enable the master SPI before enabling the slave SPI. Disable the slave SPI
before disabling the master SPI. (See
SHIFT REGISTER
MC68HC08LN56 • MC68HC708LN56 General Release Specification, Rev. 2.1
GENERATOR
MASTER MCU
BAUD RATE
Figure 11-3. Full-Duplex Master-Slave Connections
Register.) Through the SPSCK pin, the baud rate generator of the
MISO
MOSI
SPSCK
SS
Figure 11-3
NOTE
V
DD
11.13.1 SPI Control
SPSCK
MISO
MOSI
SS
Register.)
SHIFT REGISTER
SLAVE MCU
Freescale Semiconductor
11.7.2 Mode Fault