mc68hc08ln56 Freescale Semiconductor, Inc, mc68hc08ln56 Datasheet - Page 36

• Manufacturer Part Number: mc68hc08ln56
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Central Processing Unit (CPU)
3.3.5 Condition Code Register
The 8-bit condition code register (CCR) contains the interrupt mask and five flags that indicate the results
of the instruction just executed. Bits 6 and 5 are set permanently to logic one. The following paragraphs
describe the functions of the condition code register.
V — Overflow Flag
H — Half-Carry Flag
I — Interrupt Mask
N — Negative flag
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The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch
instructions BGT, BGE, BLE, and BLT use the overflow flag.
The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an ADD
or ADC operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic operations.
The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor.
When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled
when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched.
After the I bit is cleared, the highest-priority interrupt request is serviced first.
A return from interrupt (RTI) instruction pulls the CPU registers from the stack and restores the
interrupt mask from the stack. After any reset, the interrupt mask is set and can only be cleared by the
clear interrupt mask software instruction (CLI).
The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation
produces a negative result, setting bit 7 of the result.
1 = Overflow
0 = No overflow
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
1 = Interrupts disabled
0 = Interrupts enabled
1 = Negative result
0 = Non-negative result
Reset:
Read:
Write:
To maintain M6805 compatibility, the upper byte of the index register (H) is
not stacked automatically. If the interrupt service routine modifies H, then
the user must stack and unstack H using the PSHH and PULH instructions.
CCR
MC68HC08LN56 • MC68HC708LN56 General Release Specification, Rev. 2.1
X = Indeterminate
Bit 7
X
V
Figure 3-6. Condition Code Register (CCR)
6
1
1
5
1
1
NOTE
H
X
4
3
1
I
N
X
2
X
1
Z
Freescale Semiconductor
Bit 0
C
X