mc68hc08ln56 Freescale Semiconductor, Inc, mc68hc08ln56 Datasheet - Page 176

• Manufacturer Part Number: mc68hc08ln56
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

I/O Ports
TCLK — Timer Clock Input
TxD — SCI Transmit Data Output
RxD — SCI Receive Data Input
13.6.2 Data Direction Register E
Data direction register E determines whether each port E pin is an input or an output. Writing a logic one
to a DDRE bit enables the output buffer for the corresponding port E pin; a logic zero disables the output
buffer.
DDRE[6:0] — Data Direction Register E Bits
Figure 13-15
176
The PTE4/TCLK pin is the external clock input for the TIM. The pre-scaler select bits, PS[2:0], select
PTE4/TCLK as the TIM clock input. See
as the TIM clock, PTE4/TCLK is available for general-purpose I/O.
The PTE5/TxD pin is the transmit data output for the SCI module. When the enable SCI bit, ENSCI, is
clear, the SCI module is disabled, and the PTE5/TxD pin is available for general-purpose I/O. See
Chapter 12 Serial Communications Interface Module
The PTE7/RxD pin is the receive data input for the SCI module. When the enable SCI bit, ENSCI, is
clear, the SCI module is disabled, and the PTE1/RxD pin is available for general-purpose I/O. See
Chapter 12 Serial Communications Interface Module
These read/write bits control port E data direction. Reset clears DDRE[6:0], configuring all port E pins
as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
shows the port E I/O logic.
Data direction register E (DDRE) does not affect the data direction of port
E pins that are being used by the SCI module. However, the DDRE bits
always determine whether reading port E returns the states of the latches
or the states of the pins. See
Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
MC68HC08LN56 • MC68HC708LN56 General Release Specification, Rev. 2.1
READ DDRE ($000C)
WRITE DDRE ($000C)
WRITE PTE ($0008)
READ PTE ($0008)
RESET
Figure 13-15. Port E I/O Circuit
Chapter 10 Timer Interface Module
Table
NOTE
NOTE
DDREx
PTEx
13-6.
(SCI).
(SCI).
(TIM). When not selected
Freescale Semiconductor
PTEx