mc68hc08ln56 Freescale Semiconductor, Inc, mc68hc08ln56 Datasheet - Page 119

• Manufacturer Part Number: mc68hc08ln56
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

SPI. (See
SPSCK edge. Therefore the slave uses the first SPSCK edge as a start transmission signal. The SS pin
can remain low between transmissions. This format may be preferable in systems having only one master
and only one slave driving the MISO data line.
When CPHA = 1 for a slave, the first edge of the SPSCK indicates the beginning of the transmission. This
causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the
transmission begins, no new data is allowed into the shift register from the transmit data register.
Therefore, the SPI data register of the slave must be loaded with transmit data before the first edge of
SPSCK. Any data written after the first edge is stored in the transmit data register and transferred to the
shift register after the current transmission.
11.5.4 Transmission Initiation Latency
When the SPI is configured as a master (SPMSTR = 1), writing to the SPDR starts a transmission. CPHA
has no effect on the delay to the start of the transmission, but it does affect the initial state of the SPSCK
signal. When CPHA = 0, the SPSCK signal remains inactive for the first half of the first SPSCK cycle.
When CPHA = 1, the first SPSCK cycle begins with an edge on the SPSCK line from its inactive to its
active level. The SPI clock rate (selected by SPR1:SPR0) affects the delay from the write to SPDR and
the start of the SPI transmission. (See
derivative of the internal MCU clock. To conserve power, it is enabled only when both the SPE and
SPMSTR bits are set. SPSCK edges occur halfway through the low time of the internal MCU clock. Since
the SPI clock is free-running, it is uncertain where the write to the SPDR occurs relative to the slower
SPSCK. This uncertainty causes the variation in the initiation delay shown in
no longer than a single SPI bit time. That is, the maximum delay is two MCU bus cycles for DIV2, eight
MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128.
11.6 Queuing Transmission Data
The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI
configured as a master, a queued data byte is transmitted immediately after the previous transmission
has completed. The SPI transmitter empty flag (SPTE) indicates when the transmit data buffer is ready
to accept new data. Write to the transmit data register only when the SPTE bit is high.
the timing associated with doing back-to-back transmissions with the SPI (SPSCK has CPHA:
CPOL = 1:0).
Freescale Semiconductor
11.7.2 Mode Fault
(FOR REFERENCE)
CAPTURE STROBE
SPSCK (CPOL = 0)
SPSCK (CPOL =1)
(FROM MASTER)
SPSCK CYCLE #
SS (TO SLAVE)
(FROM SLAVE)
MC68HC08LN56 • MC68HC708LN56 General Release Specification, Rev. 2.1
MOSI
MISO
Figure 11-6. Transmission Format (CPHA = 1)
Error.) When CPHA = 1, the master begins driving its MOSI pin on the first
MSB
MSB
1
Figure
BIT 6
BIT 6
2
11-7.) The internal SPI clock in the master is a free-running
BIT 5
BIT 5
3
BIT 4
BIT 4
4
BIT 3
BIT 3
5
BIT 2
BIT 2
6
BIT 1
BIT 1
7
Figure
Queuing Transmission Data
LSB
8
LSB
11-7. This delay is
Figure 11-8
shows
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