mc68hc08ln56 Freescale Semiconductor, Inc, mc68hc08ln56 Datasheet - Page 225

• Manufacturer Part Number: mc68hc08ln56
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

21.3.1 Entering Monitor Mode
Table 21-1
CGMOUT/2 is the internal bus clock frequency. If PTC3 is low upon monitor mode entry, CGMOUT is
equal to the frequency of CGMXCLK, which is a buffered version of the clock on the OSC1 pin. The bus
frequency in this case is a divide-by-two of the input clock. If PTC3 is high upon monitor mode entry, the
bus frequency will be a divide-by-four of the input clock if the PLL is not engaged. The PLL can be
engaged to multiply the bus frequency by programming the CGM. Refer to
Module (CGMB)
one during monitor mode entry, and the bus frequency will be a divide-by-four of CGMVCLK, the output
clock of the PLL.
Enter monitor mode with the pin configuration shown above by pulling RST low and then high. The rising
edge of RST latches monitor mode. Once monitor mode is latched, the values on the specified pins can
change.
Once out of reset, the MCU monitor mode firmware then sends a break signal (10 consecutive logic zeros)
to the host computer, indicating that it is ready to receive a command. The break signal also serves as a
timing reference to allow the host to determine the necessary baud rate.
Monitor mode uses different vectors for reset, SWI, and a break interrupt than those used in user mode.
The alternate vectors are in the $FE page instead of the $FF page, and allow code execution from the
internal monitor firmware instead of user code.
When the host computer has completed downloading code into the MCU RAM, this code can be executed
by driving PTA0 low while asserting RST low and then high. The internal monitor ROM firmware will
interpret the low on PTA0 as an indication to jump RAM, and execution control will then continue from
RAM. The location jumped to is always the second byte of RAM (i.e. the first RAM byte address + 1).
Execution of an SWI from the downloaded code will return program control to the internal monitor ROM
firmware. Alternatively, the host can send a RUN command, which executes an RTI, and this can be used
to send control to the address on the stack pointer.
The COP module is disabled in monitor mode as long as V
or the RST pin. (See
operation.)
Freescale Semiconductor
IRQ1/V
V
V
DD
DD
Pin
shows the pin conditions for entering monitor mode.
+ V
+ V
PP
Holding the PTC3 pin low when entering monitor mode causes a bypass of
a divide-by-two stage in the oscillator. In this case the CGMOUT frequency
is equal to the CGMXCLK (external clock) frequency. The OSC1 signal
must have a 50% duty cycle at maximum bus frequency.
HI
HI
for information on how to program the PLL. When the PLL is used, PTC3 must be logic
MC68HC08LN56 • MC68HC708LN56 General Release Specification, Rev. 2.1
PTC0
Pin
1
1
Chapter 5 System Integration Module (SIM)
PTC1
Pin
0
0
PTA0
Pin
1
1
Table 21-1. Mode Selection
PTC3
Pin
1
0
NOTE
Monitor
Monitor
Mode
DD
CGMXCLK
---------------------------- -
+ V
2
HI
for more information on modes of
CGMXCLK
CGMOUT
is applied to either the IRQ1/V
or
CGMVCLK
---------------------------- -
Chapter 4 Clock Generator
2
Functional Description
Frequency
CGMOUT
------------------------- -
CGMOUT
------------------------- -
Bus
2
2
PP
pin
225