mc68hc08ln56 Freescale Semiconductor, Inc, mc68hc08ln56 Datasheet - Page 102

• Manufacturer Part Number: mc68hc08ln56
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Timer Interface Module (TIM)
Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel
0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control register 0
(TSCR0) controls and monitors the PWM signal from the linked channels. MS0B takes priority over MS0A.
Setting MS2B links channels 2 and 3 and configures them for buffered PWM operation. The TIM channel
2 registers (TCH2H:TCH2L) initially control the PWM output. TIM status control register 2 (TSCR2)
controls and monitors the PWM signal from the linked channels. MS2B takes priority over MS2A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output
compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle
output.
Setting the channel x maximum duty cycle bit (CHxMAX) and clearing the TOVx bit generates a 100%
duty cycle output. (See
10.4 Interrupts
The following TIM sources can generate interrupt requests:
10.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power- consumption standby modes.
10.5.1 Wait Mode
The TIM remains active after the execution of a WAIT instruction. In wait mode the TIM registers are not
accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait
mode.
If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before
executing the WAIT instruction.
The DMA can service the TIM without exiting wait mode.
102
5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP.
•
•
TIM overflow flag (TOF) — The TOF bit is set when the TIM counter value rolls over to $0000 after
matching the value in the TIM counter modulo registers. The TIM overflow interrupt enable bit,
TOIE, enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and
control register.
TIM channel flags (CH3F:CH0F) — The CHxF bit is set when an input capture or output compare
occurs on channel x. Channel x TIM CPU interrupt requests and TIM DMA service requests are
controlled by the channel x interrupt enable bit, CHxIE, and the channel x DMA select bit, DMAxS.
Channel x TIM CPU interrupt requests are enabled when CHxIE:DMAxS = 1:0. Channel x
TIM DMA service requests are enabled when CHxIE:DMAxS = 1:1. CHxF and CHxIE are in the
TIM channel x status and control register. DMAxS is in the TIM DMA select register.
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
MC68HC08LN56 • MC68HC708LN56 General Release Specification, Rev. 2.1
10.8.5 TIM Channel Status and Control Registers
(TSC0:TSC3).)
Freescale Semiconductor