mc68hc08ln56 Freescale Semiconductor, Inc, mc68hc08ln56 Datasheet - Page 159

• Manufacturer Part Number: mc68hc08ln56
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

OR — Receiver Overrun Bit
Freescale Semiconductor
After the receiver is enabled, it must receive a valid character that sets the SCRF bit before an idle
condition can set the IDLE bit. Also, after the IDLE bit has been cleared, a valid character must again
set the SCRF bit before an idle condition can set the IDLE bit. Reset clears the IDLE bit.
This clearable, read-only bit is set when software fails to read the SCDR before the receive shift
register receives the next character. The OR bit generates an SCI error CPU interrupt request if the
ORIE bit in SCC3 is also set. The data in the shift register is lost, but the data already in the SCDR is
not affected. Clear the OR bit by reading SCS1 with OR set and then reading the SCDR. Reset clears
the OR bit.
Software latency may allow an overrun to occur between reads of SCS1 and SCDR in the flag-clearing
sequence.
caused by a delayed flag-clearing sequence. The delayed read of SCDR does not clear the OR bit
because OR was not set when SCS1 was read. Byte 2 caused the overrun and is lost. The next
flag-clearing sequence reads byte 3 in the SCDR instead of byte 2.
In applications that are subject to software latency or in which it is important to know which byte is lost
due to an overrun, the flag-clearing routine can check the OR bit in a second read of SCS1 after
reading the data register.
1 = Receiver input idle
0 = Receiver input active (or idle since the IDLE bit was cleared)
1 = Receive shift register full and SCRF = 1
0 = No receiver overrun
Figure 12-15
BYTE 1
BYTE 1
MC68HC08LN56 • MC68HC708LN56 General Release Specification, Rev. 2.1
READ SCS1
READ SCDR
shows the normal flag-clearing sequence and an example of an overrun
SCRF = 1
(BYTE 1)
Figure 12-15. Flag Clearing Sequence
OR = 0
READ SCDR
READ SCS1
BYTE 2
BYTE 2
DELAYED FLAG CLEARING SEQUENCE
SCRF = 1
NORMAL FLAG CLEARING SEQUENCE
(BYTE 1)
OR = 0
READ SCDR
READ SCS1
SCRF = 1
(BYTE 2)
OR = 0
BYTE 3
BYTE 3
READ SCDR
READ SCDR
READ SCS1
READ SCS1
SCRF = 1
SCRF = 1
(BYTE 3)
(BYTE 3)
OR = 1
OR = 0
BYTE 4
BYTE 4
I/O Registers
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