mc68hc08ln56 Freescale Semiconductor, Inc, mc68hc08ln56 Datasheet - Page 173

• Manufacturer Part Number: mc68hc08ln56
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

13.5 Port D
Port D is an 8-bit special function port that shares all eight of its pins with two serial peripheral interface
modules (SPI).
13.5.1 Port D Data Register
The port D data register contains a data latch for each of the eight port D pins.
PTD[7:0] — Port D Data Bits
MISO1 — Master In/Slave Out1
MOSI1 — Master Out/Slave In 1
SS1 — Slave Select 1
SPSCK1 — SPI1 Serial Clock
SPSCK2 — SPI2 Serial Clock
SS2 — Slave Select 2
Freescale Semiconductor
These read/write bits are software-programmable. Data direction of each port D pin is under the control
of the corresponding bit in data direction register D. Reset has no effect on port D data.
The PTD0/MISO1 pin is the master in/slave out terminal of the SPI1 module. When the SPI enable bit,
SPE, is clear, the SPI module is disabled, and the PTD0/MISO1 pin is available for general-purpose
I/O.
Data direction register D (DDRD) does not affect the data direction of port D pins that are being used
by the SPI1 module. However, the DDRD bits always determine whether reading port D returns the
states of the latches or the states of the pins. See
The PTD1/MOSI1 pin is the master out/slave in terminal of the SPI1 module. When the SPE bit is clear,
the PTD1/MOSI1 pin is available for general-purpose I/O.
The PTD2/SS1 pin is the slave select input of the SPI1 module. When the SPE bit is clear, or when
the SPI master bit, SPMSTR, is set, the PTD2/SS1 pin is available for general-purpose I/O. When the
SPI is enabled, the DDRB2 bit in data direction register B (DDRB) has no effect on the PTD2/SS1 pin.
The PTD3/SPSCK1 pin is the serial clock input of the SPI1 module. When the SPE bit is clear, the
PTD3/SPSCK1 pin is available for general-purpose I/O.
The PTD4/SPSCK2 pin is the serial clock input of the SPI2 module. When the SPE bit is clear, the
PTD4/SPSCK2 pin is available for general-purpose I/O.
The PTD5/SS2 pin is the slave select input of the SPI2 module. When the SPE bit is clear, or when
the SPI master bit, SPMSTR, is set, the PTD5/SS2 pin is available for general-purpose I/O. When the
SPI2 is enabled, the DDRD5 bit in data direction register D(DDRD) has no effect on the PTD2/SS1 pin.
Alternate Function:
MC68HC08LN56 • MC68HC708LN56 General Release Specification, Rev. 2.1
Reset:
$0003
Read:
Write:
PTD
MISO2
PTD7
Bit 7
Figure 13-11. Port D Data Register (PTD)
MOSI2
PTD6
6
PTD5
SS2
5
SPSCK2
Unaffected by reset
PTD4
Table
4
13-5.
SPSCK1
PTD3
3
PTD2
SS1
2
MOSI1
PTD1
1
MISO1
PTD0
Bit 0
Port D
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