mc68hc08ln56 Freescale Semiconductor, Inc, mc68hc08ln56 Datasheet - Page 122

• Manufacturer Part Number: mc68hc08ln56
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Serial Peripheral Interface Module (SPI)
MODF or OVRF individually to generate a receiver/error CPU interrupt request. However, leaving
MODFEN low prevents MODF from being set.
When the DMA is enabled to service the SPRF flag, it clears SPRF when it reads the receive data register.
The OVRF bit, however, still requires the two-step clearing mechanism of reading the flag when it is set
and then reading the receive data register. In this way, the DMA cannot directly clear the OVRF. However,
if the CPU reads the SPI status and control register with the OVRF bit set, and then the DMA reads the
receive data register, the OVRF bit is cleared.
OVRF interrupt requests to the CPU should be enabled when using the DMA to service the SPRF if there
is any chance that the overflow condition might occur. (See
SPRF bit, no new data transfers from the shift register to the receive data register with the OVRF bit high.
This means that no new SPRF interrupt requests are generated until the CPU clears the OVRF bit. If the
CPU reads the data register to clear the OVRF bit, it could clear a pending SPRF service request to the
DMA.
The overflow service routine may need to disable the DMA and manually recover since an overflow
indicates the loss of data. Loss of data may prevent the DMA from reaching its byte count.
If your application requires the DMA to bring the MCU out of wait mode, enable the OVRF bit to generate
CPU interrupt requests. An overflow condition in wait mode can cause the MCU to hang in wait mode
because the DMA cannot reach its byte count. Setting the error interrupt enable bit (ERRIE) in the SPI
status and control register enables the OVRF bit to bring the MCU out of wait mode.
If the CPU SPRF interrupt is enabled and the OVRF interrupt is not, watch for an overflow condition.
Figure 11-10
possible to read the SPSCR and SPDR to clear the SPRF without problems. However, as illustrated by
the second transmission example, the OVRF bit can be set in between the time that SPSCR and SPDR
are read.
In this case, an overflow can easily be missed. Since no more SPRF interrupts can be generated until this
OVRF is serviced, it is not obvious that bytes are being lost as more transmissions are completed. To
prevent this, either enable the OVRF interrupt or do another read of the SPSCR following the read of the
SPDR. This ensures that the OVRF was not set before the SPRF was cleared and that future
122
SPI RECEIVE
shows how it is possible to miss an overflow. The first part of
COMPLETE
DMA READ
OF SPDR
OVRF
SPRF
MC68HC08LN56 • MC68HC708LN56 General Release Specification, Rev. 2.1
Figure 11-9. Overflow Condition with DMA Service of SPRF
1
2
3
BYTE 1
DMA READS BYTE 1, CLEARING SPRF BIT.
BYTE 1 TRANSFERS FROM SHIFT
REGISTER TO DATA REGISTER,
SETTING SPRF BIT.
BYTE 2 TRANSFERS FROM SHIFT
REGISTER TO DATA REGISTER,
SETTING SPRF BIT.
1
2
BYTE 2
3
BYTE 3
4
4
5
6
Figure
BYTE 3 CAUSES OVERFLOW. BYTE 3 IS LOST.
DMA READS BYTE 2, CLEARING SPRF BIT.
BYTE 4 IS LOST. NO NEW SPRF DMA SERVICE
REQUESTS AND NO TRANSFERS TO DATA
REGISTER UNTIL OVRF IS CLEARED.
5
11-9.) Even if the DMA clears the
BYTE 4
6
Figure 11-10
Freescale Semiconductor
BYTE 5
shows how it is