mc68hc08ln56 Freescale Semiconductor, Inc, mc68hc08ln56 Datasheet - Page 65

• Manufacturer Part Number: mc68hc08ln56
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals and other chips within a system
built around the MCU.
5.3.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate
that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out
4096 CGMXCLK cycles. Sixty-four CGMXCLK cycles later, the CPU and memories are released from
reset to allow the reset vector sequence to occur.
At power-on, these events occur:
Freescale Semiconductor
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A POR pulse is generated.
The internal reset signal is asserted.
The SIM enables CGMOUT.
Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow
stabilization of the oscillator.
The RST pin is driven low during the oscillator stabilization time.
The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are
cleared.
CGMXCLK
IRST
RST
IAB
MC68HC08LN56 • MC68HC708LN56 General Release Specification, Rev. 2.1
Figure 5-6. Sources of Internal Reset
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
RST PULLED LOW BY MCU
Figure 5-5. Internal Reset Timing
32 CYCLES
COPRST
POR
LVI
INTERNAL RESET
32 CYCLES
VECTOR HIGH
Reset and System Initialization
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