mc68hc08ln56 Freescale Semiconductor, Inc, mc68hc08ln56 Datasheet - Page 62

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mc68hc08ln56

Manufacturer Part Number
mc68hc08ln56
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
System Integration Module (SIM)
62
PIN LOGIC
RESET
Signal Name
CGMXCLK
CGMVCLK
CGMOUT
PORRST
IRST
R/W
IAB
IDB
MC68HC08LN56 • MC68HC708LN56 General Release Specification, Rev. 2.1
SIM RESET STATUS REGISTER
Buffered version of OSC1 from clock generator module (CGM)
PLL output
PLL-based or OSC1-based clock output from CGM module
(Bus clock = CGMOUT divided by two)
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
RESET PIN CONTROL
Table 5-1. Signal Name Conventions
POR CONTROL
STOP/WAIT
CONTROL
CONTROL
AND PRIORITY DECODE
INTERRUPT CONTROL
CLOCK
Figure 5-2. SIM Block Diagram
CLOCK GENERATORS
RESET
COUNTER
SIM
÷ 2
CONTROL
Description
MASTER
RESET
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO CGM)
COP CLOCK
CGMXCLK (FROM CGM)
CGMOUT (FROM CGM)
INTERNAL CLOCKS
LVI (FROM LVI MODULE)
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP (FROM COP MODULE)
CPU INTERFACE
INTERRUPT SOURCES
Freescale Semiconductor

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