mc68hc08ln56 Freescale Semiconductor, Inc, mc68hc08ln56 Datasheet - Page 103

• Manufacturer Part Number: mc68hc08ln56
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

10.5.2 Stop Mode
The TIM is inactive after the execution of a STOP instruction. The STOP instruction does not affect
register conditions or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode
after an external interrupt.
10.6 TIM During Break Interrupts
A break interrupt stops the TIM counter.
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. See
To allow software to clear status bits during a break interrupt, write a logic one to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic zero to the BCFE bit. With BCFE at logic zero
(its default state), software can read and write I/O registers during the break state without affecting status
bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on
such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic zero.
After the break, doing the second step clears the status bit.
10.7 I/O Signals
Port E shares five of its pins with the TIM. PTE4/TCLK is an external clock input to the TIM prescaler. The
four TIM channel I/O pins are PTE0/TCH0, PTE1/TCH1, PTE2/TCH2, and PTE3/TCH3.
10.7.1 TIM Clock Pin (PTE4/TCLK)
PTE4/TCLK is an external clock input that can be the clock source for the TIM counter instead of the
prescaled internal bus clock. Select the PTE4/TCLK input by writing logic ones to the three prescaler
select bits, PS[2:0]. See
TCLK
The maximum TCLK frequency is:
PTE4/TCLK is available as a general-purpose I/O pin when not used as the TIM clock input. When the
PTE4/TCLK pin is the TIM clock input, it is an input regardless of the state of the DDRE3 bit in data
direction register E.
10.7.2 TIM Channel I/O Pins (PTE0/TCH0:PTE3/TCH3)
Each channel I/O pin is programmable independently as an input capture pin or an output compare pin.
PTE0/TCH0 and PTE2/TCH2 can be configured as buffered output compare or buffered PWM pins.
Freescale Semiconductor
bus frequency ÷ 2
LMIN
or TCLK
HMIN
MC68HC08LN56 • MC68HC708LN56 General Release Specification, Rev. 2.1
, is:
10.8.1 TIM Status and Control Register
------------------------------------ -
bus frequency
5.7.3 SIM Break Flag Control Register
1
+
t
SU
(TSC). The minimum TCLK pulse width,
(SBFCR).
TIM During Break Interrupts
103