mc68hc08ln56 Freescale Semiconductor, Inc, mc68hc08ln56 Datasheet - Page 127

• Manufacturer Part Number: mc68hc08ln56
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

The following items are reset only by a system reset:
By not resetting the control bits when SPE is low, the user can clear SPE between transmissions without
having to set all control bits again when SPE is set back high for the next transmission.
By not resetting the SPRF, OVRF, and MODF flags, the user can still service these interrupts after the
SPI has been disabled. The user can disable the SPI by writing 0 to the SPE bit. The SPI can also be
disabled by a mode fault occuring in an SPI that was configured as a master with the MODFEN bit set.
11.10 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power-consumption standby modes.
11.10.1 Wait Mode
The SPI module remains active after the execution of a WAIT instruction. In wait mode the SPI module
registers are not accessible by the CPU. Any enabled CPU interrupt request from the SPI module can
bring the MCU out of wait mode.
If SPI module functions are not required during wait mode, reduce power consumption by disabling the
SPI module before executing the WAIT instruction.
The DMA can service DMA service requests generated by the SPTE and SPRF flags without exiting wait
mode. To exit wait mode when an overflow condition occurs, enable the OVRF bit to generate CPU
interrupt requests by setting the error interrupt enable bit (ERRIE). (See
11.10.2 Stop Mode
The SPI module is inactive after the execution of a STOP instruction. The STOP instruction does not
affect register conditions. SPI operation resumes after an external interrupt. If stop mode is exited by
reset, any transfer in progress is aborted, and the SPI is reset.
11.11 SPI During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See
To allow software to clear status bits during a break interrupt, write a logic one to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic zero to the BCFE bit. With BCFE at logic zero
(its default state), software can read and write I/O registers during the break state without affecting status
bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on
such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic zero.
After the break, doing the second step clears the status bit.
Freescale Semiconductor
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All control bits in the SPCR register
All control bits in the SPSCR register (MODFEN, ERRIE, SPR1, and SPR0)
The status flags SPRF, OVRF, and MODF
MC68HC08LN56 • MC68HC708LN56 General Release Specification, Rev. 2.1
Chapter 5 System Integration Module
11.8
Interrupts.)
(SIM).)
Low-Power Modes
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