mc68hc08ln56 Freescale Semiconductor, Inc, mc68hc08ln56 Datasheet - Page 108

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mc68hc08ln56

Manufacturer Part Number
mc68hc08ln56
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Timer Interface Module (TIM)
10.8.5 TIM Channel Status and Control Registers (TSC0:TSC3)
Each of the TIM channel status and control registers:
CHxF — Channel x Flag Bit
108
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIM counter registers matches the value in the TIM channel x registers.
When TIM CPU interrupt requests are enabled (CHxIE:DMAxS = 1:0), clear CHxF by reading TIM
channel x status and control register with CHxF set and then writing a logic zero to CHxF. If another
interrupt request occurs before the clearing sequence is complete, then writing logic zero to CHxF has
no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF.
Flags input captures and output compares
Enables input capture and output compare interrupts
Selects input capture, output compare, or PWM operation
Selects high, low, or toggling output on output compare
Selects rising edge, falling edge, or any edge as the active input capture trigger
Selects output toggling on TIM overflow
Selects 100% PWM duty cycle
Selects buffered or unbuffered output compare/PWM operation
$002C
$0026
$0029
$002F
TSC0
TSC1
TSC2
TSC3
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
MC68HC08LN56 • MC68HC708LN56 General Release Specification, Rev. 2.1
CH0F
CH1F
CH2F
CH3F
Bit 7
Bit 7
Bit 7
Bit 7
0
0
0
0
0
0
0
0
= Unimplemented
CH0IE
CH1IE
CH2IE
CH3IE
Figure 10-7. TIM Channel Status and
6
0
6
0
6
0
6
0
Control Registers (TSC0:TSC3)
MS0B
MS2B
5
0
5
0
0
5
0
5
0
0
MS0A
MS1A
MS2A
MS3A
4
0
4
0
4
0
4
0
ELS0B
ELS1B
ELS2B
ELS3B
3
0
3
0
3
0
3
0
ELS0A
ELS1A
ELS2A
ELS3A
2
0
2
0
2
0
2
0
TOV0
TOV1
TOV2
TOV3
1
0
1
0
1
0
1
0
Freescale Semiconductor
CH0MAX
CH1MAX
CH2MAX
CH3MAX
Bit 0
Bit 0
Bit 0
Bit 0
0
0
0
0

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