mc68hc08ln56 Freescale Semiconductor, Inc, mc68hc08ln56 Datasheet - Page 149

• Manufacturer Part Number: mc68hc08ln56
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

12.4.3.7 Receiver Interrupts
The following sources can generate CPU interrupt requests from the SCI receiver:
12.4.3.8 Error Interrupts
The following receiver error flags in SCS1 can generate CPU interrupt requests:
12.4.3.9 Error Flags During DMA Service Requests
When the DMA is servicing the SCI receiver, it clears the SCRF bit when it reads the SCI data register.
The DMA does not clear the other status bits (BKF or RPF), nor does it clear error flags (OR, NF, FE, and
PE). To clear error flags while the DMA is servicing the receiver, enable SCI error CPU interrupts and
clear the bits in an interrupt routine. The application may require retransmission in case of error. If the
application requires the receptions to continue, note the following latency considerations:
Freescale Semiconductor
1. If interrupt latency is short enough for an error bit to be serviced before the next SCRF, then it can
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SCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that the receive shift register has
transferred a character to the SCDR. SCRF can generate a receiver CPU interrupt request or a
receiver DMA service request. Setting the SCI receive interrupt enable bit, SCRIE, in SCC2
enables the SCRF bit to generate receiver CPU interrupts. Setting both the SCRIE bit and the DMA
receive enable bit, DMARE, in SCC3 enables receiver DMA service requests and disables receiver
CPU interrupt requests.
Idle input (IDLE) — The IDLE bit in SCS1 indicates that 10 or 11 consecutive logic ones shifted in
from the PTE6/RxD pin. The idle line interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to
generate CPU interrupt requests.
Receiver overrun (OR) — The OR bit indicates that the receive shift register shifted in a new
character before the previous character was read from the SCDR. The previous character remains
in the SCDR, and the new character is lost. The overrun interrupt enable bit, ORIE, in SCC3
enables OR to generate SCI error CPU interrupt requests.
Noise flag (NF) — The NF bit is set when the SCI detects noise on incoming data or break
characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in SCC3
enables NF to generate SCI error CPU interrupt requests.
Framing error (FE) — The FE bit in SCS1 is set when a logic zero occurs where the receiver
expects a stop bit. The framing error interrupt enable bit, FEIE, in SCC3 enables FE to generate
SCI error CPU interrupt requests.
Parity error (PE) — The PE bit in SCS1 is set when the SCI detects a parity error in incoming data.
The parity error interrupt enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU interrupt
requests.
be determined which byte caused the error. If interrupt latency is long enough for a new SCRF to
occur before servicing an error bit, then:
a. It cannot be determined whether the error bit being serviced is due to the byte in the SCI data
register or to a previous byte. Multiple errors can accumulate that correspond to different
bytes. In a message-based system, you may have to repeat the entire message.
When receiver DMA service requests are enabled (DMARE = 1), then
receiver CPU interrupt requests are disabled.
MC68HC08LN56 • MC68HC708LN56 General Release Specification, Rev. 2.1
NOTE
Functional Description
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